Delay locked looped circuits and methods of operation thereof

Details Delay locked looped circuits and methods of operation thereof Delay locked looped circuits and methods of operation thereof

2000-01-18

2001-10-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C327S012000, C327S161000

Reexamination Certificate

active

06304116

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 99-2404, filed Jan. 26, 1999, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to apparatus and methods for synchronizing clock signals in integrated circuit devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices such as microprocessors, memories and other peripheral circuits typically operate in a synchronized fashion at very high speeds. For example, such devices may operate in synchronization with an external clock signal using an internal clock signal which is delayed for a predetermined length of time with respect to the external clock signal. The performance of such devices may be subject to degradation at the high clock frequencies associated with high speed operations. For example, the length of time used for outputting data after the external clock signal is applied, sometimes referred to as the output data access time tAC, may be lengthened. Thus, such a device often includes one or more circuits for generating clock signals synchronized to a reference clock signal. One example of a circuit for synchronizing an external clock and an internal clock is a delay locked loop (DLL) which may reduce deterioration of the operational performance of the integrated circuit device at high frequencies. The DLL is also widely used for a clock recovery systems, time-to-digital conversion circuits, and high speed serial links.
A typically DLL circuit generates a delayed clock signal from a reference clock signal, with the delayed clock signal typically being used as a reference signal for operation of devices. A typically DLL circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal. A DLL may be implemented as an analog DLL, a digital DLL, or a hybrid DLL may be used. The analog DLL typically has good jitter characteristics but may be locked into an incorrect (false) state in which the internal clock signal is delayed by one or even more periods with respect to an external clock signal. False locking is generally undesirable due to potentially increased noise susceptibility as well as jitter accumulation.
FIG. 1
illustrates a prior art analog DLL. As shown in
FIG. 1
, the prior art analog DLL includes a delay line
11
including a plurality of unit delays d
1
through dn which are connected in series. A phase detector
13
receives an input clock signal CLKIN and an output clock signal CLKOUT of the delay line
11
to detect the difference in phase between them. A charge pump circuit
15
generates a control voltage to vary the delay time of the unit delays d
1
through dn in response to output signals FWD and BCK from the phase detector
13
. In the illustrated DLL, the input clock signal CLKIN may be an external clock signal and the output clock signal CLKOUT may be an internal clock signal.
The phase detector
13
may be a reset-set (RS) type phase detector or a three-state phase frequency detector (PFD). Operational timing diagrams of an RS type phase detector are illustrated in
FIGS. 2
a
and
2
b
. Operational timing diagrams of the three-state PFD are illustrated in
FIGS. 3
a
and
3
b
.
FIGS. 2
a
and
3
a
show the timing for the case in which the total delay tTOTAL of the delay line
11
is less than the period T of the input clock signal CLKIN. In other words, for tTOTAL=&Dgr;.
FIGS. 2B and 3B
illustrate timing for the case in which the total delay tTOTAL of the delay line
11
is more than the period T of the input clock signal CLKIN. In other words, for tTOTAL=&Dgr;+T.
In the illustrated analog DLL using the RS type phase detector or the three-state PFD as the phase detector
13
, when tTOTAL=&Dgr;, the output signal FWD controls the charge pump circuit
15
to increase the delay time of the unit delays d
1
through dn, so that the analog DLL may be locked to provide a delay time of tTOTAL=T. However, when tTOTAL=&Dgr;+T, the output signals BCK and FWD are controlled in the same manner as in the case when tTOTAL=&Dgr;. As a result, the analog DLL may be maintained in a false state, i.e., locked to a delay in which tTOTAL=2T.
In other words, the RS type phase detector or the three-state PFD provides the same output signals BCK and FWD for under conditions when tTOTAL=&Dgr;+mT, where m=0, 1, 2, . . . , and, thus, when tTOTAL=&Dgr;+mT, where m=1, 2, . . . , the analog DLL is in a false state, i.e., locked to a delay condition in which tTOTAL=nT, where n=2, 3, 4, . . . , In many cases, the unit delays d
1
through dn are provided with a limited range of possible delays, therefore, a false state is most likely locked in to a condition where tTOTAL=2T.
It is known to take certain steps to limit the potential for false locking. For example, the delay time of the unit delays d
1
through dn can be initialized to a minimum or maximum value such that the analog DLL may be able to recognize whether the delay time of the unit delays d
1
through dn is to be increased or reduced to suppress false locking. However, additional circuits or an increase in locking time are typically required to implement these approaches.
SUMMARY OF THE INVENTION
The present invention provides delay locked loop circuits, phase detectors and methods for producing a delayed signal from a periodic input signal. An intermediate delay signal as well as an input signal and a delayed output signal are provided to a delay control circuit that controls the delay of a delay circuit based on a comparison of the input signal and output signal following a transition of the intermediate signal. The apparatus and methods of the present invention may thereby be able to distinguish between a case in which tTOTAL=T and tTOTAL=2T to reduce the potential for locking in a false state.
In one embodiment of the present invention a delay locked loop circuit is provided including a delay circuit that receives an input clock signal and produces an output clock signal and an intermediate clock signal that are delayed with respect to the input clock signal responsive to a delay control signal applied to the delay circuit. The intermediate clock signal is delayed less than the output clock signal. A delay control circuit, responsive to the input clock signal, the intermediate clock signal and the output clock signal, applies a delay control signal to the delay circuit based on a comparison of a transition of the output clock signal, a transition of the input clock signal and a transition of an intermediate clock signal. The delay control circuit may generate the delay control signal based on a timing of the transition of the input clock signal relative to the transition of the output clock signal following the transition of the intermediate clock signal.
In a further embodiment of the present invention, the delay control circuit includes a phase detector circuit that receives the input clock signal, the intermediate clock signal and the output clock signal and generates a first phase comparison signal when, following the transition of the intermediate clock signal, the transition of the output clock signal lags the transition of the input clock signal and a second phase comparison signal when the transition of the output clock signal leads the transition of the input clock signal. A delay control signal generating circuit applies a delay control signal to the delay circuit responsive to the phase comparison signals. The delay control signal generating circuit may be a charge pump circuit that generates the delay control signal responsive to the phase comparison signals. The first phase comparison signal and the second phase comparison signal may be a first state and a second state of a s

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