Delay locked loop with fixed angle de-skew, quick start and...

Details Delay locked loop with fixed angle de-skew, quick start and... Delay locked loop with fixed angle de-skew, quick start and...

2003-06-24

2008-03-11

Ghebretinsae, Temesghen (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C327S149000, C327S158000

Reexamination Certificate

active

07342985

ABSTRACT:
Digital delay locked loops which generate fixed angle delayed (e.g., quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature delay elements is calculated based on the number of delay elements needed to provide one or more cycles of delay, and adjusted to reflect system clock delay. The digital delay locked loop also acquires a locked state quickly by sampling more frequently before acquiring the lock than after. Furthermore, jitter is reduced by introducing hysteresis into the sampling process, and by disabling the delay element adjustment process during jitter sensitive times. Lock stability is improved by introducing hysteresis into the lock detection process.

REFERENCES:
patent: 6137325 (2000-10-01), Miller, Jr.
patent: 6201424 (2001-03-01), Harrison
patent: 6281726 (2001-08-01), Miller, Jr.
patent: 6316976 (2001-11-01), Miller, Jr. et al.
patent: 6337590 (2002-01-01), Millar
patent: 6429715 (2002-08-01), Bapat et al.
patent: 6452431 (2002-09-01), Waldrop
patent: 6469555 (2002-10-01), Lau et al.
patent: 2003/0215040 (2003-11-01), Bell et al.

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