Delay-locked loop with built-in self-test of phase margin

Details Delay-locked loop with built-in self-test of phase margin Delay-locked loop with built-in self-test of phase margin

2006-05-09

2006-05-09

Patel, Jay K. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S359000, C327S156000, C327S158000, C331S025000

Reexamination Certificate

active

07042971

ABSTRACT:
A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.

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