Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-12
2001-12-11
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S374000, C327S159000
Reexamination Certificate
active
06330296
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to signal skew corrections in signal generation circuits and more particularly to delay-locked loops which include a phase-frequency detector.
BACKGROUND OF THE INVENTION
Signal generation circuits have traditionally employed phase-locked loop (PLL) circuits to produce signals which are synchronized with an external reference signal. Alternatively, delay-locked loops (DLL) have been utilized to provide for signal skew corrections in signal generation circuits, particularly clock generation circuits.
A conventional DLL is configured as a feedback loop for tracking and controlling the signal skew. The conventional DLL typically comprises a phase-frequency detector (PFD) to compare a signal with an external reference signal. The conventional DLL also includes a voltage controlled delay line (VCDL) for receiving an input signal and providing the signal, wherein the signal is responsive to the input signal. The input signal, typically a clock signal, may be derived from the external or a system-wide reference signal. The VCDL has an adjustable signal propagation delay that varies between an upper and a lower limit as a function of a control voltage, whereby, relative to the input signal, the signal output from the VCDL is delayed by the adjustable delay.
In this case, the reference signal and the output signal have the same frequency and a relative phase shift equal to the adjustable delay. This phase shift can also be described in terms of a signal timing skew or simply the signal skew. The adjustable delay between these signals is relative since, in a given time period, the rising (or falling) edge of one signal precedes (or lags) the rising (or falling) edge of the other.
In operation, the PFD compares the reference signal and the signal output from the VCDL which is provided to the PFD through a feedback path. In response, the PFD provides one or both of “Up” and “Down” control signals having an active duration representative of the phase difference between the signals being compared. In other words, the PFD tracks the phase difference and the loop gradually reduces the timing skew between the reference signal and the signal output from the VCDL until they become more closely synchronized, that is, their respective rising edges are more closely aligned. Hence, the DLL performs a “loop tracking” function. When alignment between the rising edge of the reference signal and the output signal is achieved, the signals are synchronized and the DLL is said to be “locked”.
When, for instance, a system comprising the DLL “recovers” from a sleep or power-conservation mode, the control voltage may initially be at or close to its lower limit. In this case the VCDL may produce an adjustable delay equal or substantially close to its upper limit. When the adjustable delay provided by the VCDL is below one clock period and the PFD is in a “pump up” mode, the loop will cause the control voltage to increase, thus speeding of the delay through the VDCL. However, the only way the signals could be aligned is if the delay is zero. Since this situation is impossible, the VCDL may become stuck at an always high state causing the PFD to also get “stuck”. Under this circumstances the DLL loop tracking fails.
A conventional DLL is disclosed in U.S. Pat. No. 5, 661,419 to Raghunand Bhagwan (Bhagwan), avoids the DLL loop tracking failure when the adjustable delay provided by the VCDL is at its upper limit. Bhagwan discloses keeping the Up signal active during the time in which the VCDL is stuck, thereby permitting the VCDL to regulate the adjustable delay so that, for example, during transition from the sleep mode to normal operation mode, the adjustable delay is decreased in a predictably short time. However, conventional PFDs, including the one above-described, may also get stuck when the adjustable delay is at its lower limit while the PFD is still asserting the Up control signal.
Accordingly, what is needed is a DLL which avoids the above-identified stuck conditions. Particularly, a DLL is needed that can recover from the stuck condition in which the adjustable delay is at its lower limit and the PFD asserts the UP control signal. The DLL needs to be cost effective and easily implemented utilizing existing processes. Finally, the DLL needs to behave reliably. The present invention addresses such needs.
SUMMARY OF THE INVENTION
The present invention provides a delay-locked loop (DLL). The DLL comprises a phase-frequency detector (PFD) for receiving a reference signal. The DLL further includes a charge pump which is coupled to the PFD. The DLL also includes a loop filter which is coupled to the charge pump and the PFD. Additionally in the DLL, delay line means is coupled to the charge pump and the loop filter. The delay line means provides a feedback signal to the PFD. The DLL further includes monitor means coupled to the PFD, the charge pump and the loop filter. The monitor means is for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the PFD to enter a pump-down mode until the feedback signal is aligned with the reference signal.
An advantage of the present invention is that DLL loop tracking failures based upon a stuck condition are reliably avoided. Specifically, the DLL in accordance with the present invention can reliably recover from the stuck condition in which the adjustable delay is at its lower limit and the PFD asserts the UP control signal. Additionally, the DLL is cost effective and is easily implemented utilizing existing processes.
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Atallah Francois Ibrahim
Dieffenderfer James Norris
Diniz George
Seman David John
Bayard Emmanuel
International Business Machines - Corporation
Pham Chi
Sawyer Law Group LLP
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