Delay locked loop synthesizer with multiple outputs and...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S268000, C375S271000, C375S320000, C375S322000, C375S300000, C375S302000, C327S141000, C327S152000, C327S153000, C327S154000, C327S155000

Reexamination Certificate

active

10050233

ABSTRACT:
A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A,265B,265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.

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