Delay locked loop for use in semiconductor memory device

Details Delay locked loop for use in semiconductor memory device Delay locked loop for use in semiconductor memory device

2000-12-19

2003-04-29

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C327S158000

Reexamination Certificate

active

06556488

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; particularly to a time delay locked loop having a short locking time.
BACKGROUND OF THE INVENTION
In general, a delay locked loop represents a circuit that is used to synchronize an internal clock of a synchronous memory device with an external clock without errors. That is, since a timing delay occurs when the external clock is inputted into the inside of the memory device, the delay locked loop is used to control the timing delay to thereby synchronize the internal clock with the external clock.
Referring to
FIG. 1
, there is illustrated a block diagram of a conventional delay locked loop.
If a clock signal Clock_
1
is coupled thereto, a controllable delay chain block
100
delays the clock signal Clock_
1
by a predetermined delay time to thereby produce a delayed clock signal Delayed_clock.
The delayed clock signal Delayed_clock is fed to a pre-delay/post-delay comparison block
110
that compares the delayed clock signal Delayed_clock with a reference clock signal Reference_clock to thereby determine whether increasing or decreasing the predetermined delay time is required. Through the comparison process, the pre-delay/post-delay/comparison block
110
generates output signals Add_delay and Subtract_delay that are, in turn, fed back to the controllable delay chain block
100
so as to adjust the delay time.
The above delay and comparison processes are repeated until a delayed time of the delayed clock signal Delayed_clock is identical to that of the reference clock signal Reference_clock.
Referring to
FIG. 2
, there is shown a block diagram of a conventional time delay locked loop employing a careful delay controller.
Once a clock signal Clock_
1
is coupled thereto, a controllable delay chain block
200
generates a delayed clock signal Delayed_clock by delaying the clock signal Clock_
1
and the delayed clock signal Delayed_clock is provided to a predelay/post-delay comparison block
210
.
The pre-delay/post-delay comparison block
210
compares the delayed clock signal Delayed_clock with a reference clock signal Reference_clock so as to determine whether increasing or decreasing the delay time of the delayed clock signal Delayed_clock is necessary. As a result of the comparison process, the pre-delay/post-delay comparison block
210
produces output signals Add_delay_i and Sub_delay_i to a careful delay controller
220
.
The careful delay controller
220
is employed to preclude an incorrect determination for the delay time, wherein the incorrect determination may occur by a noise introduced by the power supply or an irregular noise at a system. That is, the delay controller
220
controls the controllable delay chain block
200
to change the delay time only when the delay time determination satisfies a predetermined standard by collecting the results of more than two continuous determination processes instead of directly applying the result of the pre-delay/post-delay comparison block
210
to change the delay time. The output signals Add_delay and Subtract_delay of the delay controller
220
are fed back to the controllable delay chain block
20
to thereby adjust the delay time.
As described above, the conventional delay locked loop of
FIG. 2
is insensitive to noise at the state when the delayed locked loop normally operates and the locking is done. However, there is a disadvantage that it takes a very long time from an initial condition in which the locking is not caused to the locking: That is, since, in order to adjust the time delay, there must be at least two determination processes for the increase or decrease in the delay time generated by the pre-delay/post-delay comparison block
210
, the time required for the locking may be much longer compared with that of using only one time of determination, as in the delay locked loop of FIG.
1
.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a time delay locked loop which classifies a locking state of the delay locked loop into a locked state and a unlocked state, and either uses a conventional time delay adjusting method in the unlocked state or reduces or eliminates a incorrect determination of the locking introduced by a noise in the locked state.
In accordance with the present invention, there is provided a delay locked loop for use in a semiconductor memory device, comprising: a controllable delay chain block for controlling a delay time of a clock signal coupled thereto; a comparison block for detecting the increase and decrease in the delay time by comparing a reference clock signal with a delayed clock signal generated from the controllable delay chain block; and an instant locking delay control block for controlling the increase and decrease in the delay time of the delay chain block in response to an output signal of the comparison block, the delayed clock signal and the reference clock signal.


REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5745533 (1998-04-01), Asada et al.
patent: 6081142 (2000-06-01), Douchi et al.

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