Delay locked loop for use in semiconductor memory device

Details Delay locked loop for use in semiconductor memory device Delay locked loop for use in semiconductor memory device

2000-12-21

2002-08-13

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S236000

Reexamination Certificate

active

06434062

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop using a bi-directional ring oscillator and a counter unit.
Description of the Prior Art
In general, a delay locked loop (DLL) circuit reduces or compensates a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error. Typically, a timing delay occurs when a clock provided externally is used within the apparatus. The delay locked loop controls the timing delay to synchronize the internal clock to the external clock.
The synchronization between the internal and external clocks requires operations of compensating a jitter of the external clock with an internal delay locked loop, controlling a time delay unit such that a delay of the internal clock is less sensitive to noise introduced by a power supply or random noises, and fastening a locking time at maximum through the control of the time delay unit. A delay locked loop with a reduced jitter and an easily controllable time delay unit to satisfy the foregoing requirements has been recently presented in ISSCC paper in 1999, entitled “A 250 Mb/s/pin 1 Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme” by NEC Corporation.
FIG. 1
is a connection diagram of a conventional linear bi-directional delay DLL proposed by NEC Corporation.
Referring to
FIG. 1
, the conventional DLL includes an input unit
100
, a first to a third D-flip flop
101
,
103
and
104
, a first inverter
102
, a dummy delay unit
105
, a first and a second AND gate
106
and
107
, a first and a second bi-directional delay block
108
and
109
, a first and a second pulse generation unit
110
and
111
, and an OR gate
112
.
The input unit
100
receives a clock signal CLK and a non-clock signal CLKB via positive and negative terminals respectively and compares received signals to produce a rising clock Rclk. The first D-flip slop
101
receives the rising clock Rclk as a clock signal and outputs a control signal with a pulse duration corresponding to one cycle of the rising clock Rclk. The first inverter
102
inverts the output of the first D-flip flop
101
to produce an inverted signal to be fed back as input to the first D-flip flop
101
. The second D-flip flop
103
receives the output of the first D-flip flop
101
and the rising clock Rclk from the input unit
100
and produces a first forward signal FWD_A having a pulse duration corresponding to one cycle of the output of the first D-flip flop
101
and a first backward signal BWD_A having an opposite phase to the first forward signal FWD_A. The third D-flip flop
104
receives an inverted value of the output of the first D-flip flop
101
and the rising clock Rclk, and produces a second forward signal FWD_B having a pulse duration corresponding to one cycle of the output of the first D-flip flop
101
and a second backward signal BWD_B having an opposite phase to the second forward signal FWD_B.
The dummy delay unit
105
delays the rising clock Rclk by a skew to compensate the clock signal CLK. The first AND gate
106
logically combines the outputs of the second D-flip flop
103
and the dummy delay unit
105
to produce a combined output. The second AND gate
107
logically combines the outputs of the third D-flip flop
104
and the dummy delay unit
105
to produce a combined output.
The first bi-directional delay block
108
including a multiplicity of unit bi-directional delays which are connected serially, receives the output of the first AND gate
106
and controls a time delay in a first or second direction under the control of the first forward signal FWD_A and the first backward signal BWD_A.
The second bi-directional delay block
109
including a multiplicity of unit bi-directional delays which are connected in series, receives the output of the second AND gate
107
and controls a time delay in the first or second direction under the control of the second forward signal FWD_B and the second backward signal BWD_B.
The first pulse generation unit
110
generates a pulse at a rising and a falling edge of the output of the first bi-directional delay block
108
. The second pulse generation unit
111
generates a pulse at a rising and a falling edge of the output of the second bi-directional delay block
109
. The OR gate
112
performs an OR operation on the outputs of the first and second pulse generation units
110
and
111
.
FIG. 2A
is a connection diagram of a conventional unit bi-directional delay, which has been proposed by FUJITSU Ltd.
As shown in
FIG. 2A
, the unit bi-directional delay proposed by FUJITSU includes four three-phase buffers
200
,
201
,
202
and
203
.
The first three-phase buffer
200
receives one of the outputs of the first and second AND gates as a first input signal A
m
to produce a second control signal B
m
, wherein the gate of a PMOS transistor is controlled by the first or second backward signal (hereinafter called BWD) and the gate of an NMOS transistor is controlled by the first or second forward signal (hereinafter called FWD). The second three-phase buffer
201
receives the second output signal B
m
, wherein the gate of a PMOS transistor is controlled by the BWD signal and the gate of an NMOS transistor is controlled by the FWD signal.
The third three-phase buffer
202
receives the output of a unit bi-directional delay at a previous stage as a second input signal B
m+1
, to produce a first output signal A
m+1
, wherein the gate of a PMOS transistor is controlled by the backward signal BWD and the gate of an NMOS transistor is controlled by the forward signal FWD.
The fourth three-phase buffer
203
receives the first output signal A
m+1
to produce the second output signal B
m
, wherein the gate of a PMOS transistor is controlled by the forward signal FWD and the gate of an NMOS transistor is controlled by the backward signal BWD.
When the forward signal FWD is logic high and the backward signal BWD is logic low, the first and second three-phase buffers
200
and
201
are activated to provide input signal to the first direction (i.e., the forward direction). When the forward signal FWD is logic low and the backward signal BWD is logic high, the third and fourth three-phase buffers
202
and
203
are activated to provide input signal to the second direction (i.e., the backward direction).
FIG. 2B
is a symbolic diagram of the unit bi-directional delay shown in FIG.
2
A. The construction and operation of the device in
FIG. 2B
is similar that of the device previously described in conjunction with FIG.
2
A and therefore a further description thereof is omitted.
FIG. 2C
is a connection diagram of the unit bi-directional delay proposed by NEC Corporation.
As shown in
FIG. 2C
, a difference between NEC and FUJITSU is that the PMOS transistor is removed in the first and fourth three-phase buffers
200
and
203
, and the NMOS transistor is removed in the second and third three-phase buffers
201
and
202
, preventing both of the first and second input signals A
m
and B
m+1
with a logic low value from being transmitted to corresponding buffers.
Although the construction of the delay locked loop described above generates a DLL signal at the rising clock Rclk of the clock signal CLK, the construction for the rising clock Rclk is similar to that of a delay locked loop for outputting the DLL signal at the falling clock Fclk of the clock signal CLK except that the output signal of the input unit
100
is a falling clock.
FIG. 3
is a timing diagram illustrating the operating principle of the first and second bi-directional delay blocks.
Referring to
FIG. 3
, in case the first forward signal FWD_A is logic high and the first backward signal BWD_A is logic low, when the first output signal A
0
_A is rendered to a logic high after a compensation skew t
dm
, the logic high signal A
0
_A is propagated

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