Delay-locked loop for differential clock signals

Details Delay-locked loop for differential clock signals Delay-locked loop for differential clock signals

2000-09-13

2004-07-20

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000, C327S159000, C327S158000, C327S237000, C327S149000, C375S371000, C375S358000, C375S373000

Reexamination Certificate

active

06765976

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits, and in particular to methods and circuitry for implementing delay-locking for two separate periodic signals using a single delay-locked loop circuit.
Delay-locked loops (DLLs) are commonly employed to generate a “clean” internal clock signal from a noisy external clock signal. Among the factors by which the performance of a DLL is typically measured are the speed of operation (i.e., the minimum number of locking cycles), jitter, the size of the circuit and power consumption. There has been a need for more efficient implementation of DLLs as operating speeds of modern integrated circuits have increased. Some circuit applications require the use of two separate clock signals. For example, the so called double data rate (DDR) or quad data rate (QDR) synchronous dynamic random access memory (SDRAM) system uses a differential pair of clock signals, CLK and CLK#, to process data. These types of circuits have conventionally used two separate DLLs for the two clock signals. This implementation results in increased overall circuit size and power consumption, therefore increasing the cost of the device.
SUMMARY OF THE INVENTION
The present invention provides a significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, the input to the DLL is controlled such that it responds to edges of both clock signals.
Accordingly, in one embodiment, the present invention provides a circuit receiving a first periodic signal CLK
1
and a second periodic signal CLK
2
, there being a phase difference between CLK
1
and CLK
2
, the circuit including a DLL having one delay path, wherein the same delay path provides delay tuning for both CLK
1
and CLK
2
.
In another embodiment, the present invention provides a method of tuning the delay of two out-of-phase periodic signals, CLK
1
and CLK
2
, including: combining CLK
1
and CLK
2
to generate a first periodic signal C_IN
1
with a rising edge determined by CLK
1
and a falling edge determined by CLK
2
; and applying C_IN
1
to a DLL having a delay path that substantially maintains the duty ratio of C_IN
1
, whereby the delay-locked loop generates output signals that are delay-tuned to CLK
1
and CLK
2
.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.


REFERENCES:
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5610543 (1997-03-01), Chang et al.
patent: 5796673 (1998-08-01), Foss et al.
patent: 5808498 (1998-09-01), Donnelly et al.
patent: 5923613 (1999-07-01), Tien et al.
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5969552 (1999-10-01), Lee et al.
patent: 5999032 (1999-12-01), Wang et al.
patent: 6043694 (2000-03-01), Dortu
patent: 6101137 (2000-08-01), Roh
patent: 6127866 (2000-10-01), Chu et al.
patent: 6205191 (2001-03-01), Portmann et al.
patent: 6265903 (2001-07-01), Takahashi
patent: 6285625 (2001-09-01), Vogley
patent: 6539072 (2003-03-01), Donnelly et al.

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