Delay locked loop for detecting the phase difference of two sign

Details Delay locked loop for detecting the phase difference of two sign Delay locked loop for detecting the phase difference of two sign

1994-03-08

1995-08-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

36518912, 365233, 327271, 327281, G11C 700

Patent

active

054405157

ABSTRACT:
A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

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F. E. Sakalay, "Memory Strobe Control," IBM Technical Disclosure, vol. 7, No. 6, Nov. 1964, p. 448.
Terry I. Chappell et al., "A 2ns Cycle, 4ns Access 514kb CMOS ECL SRAM", Feb., 1991 IEEE International Solid-State Circuits Conference, pp. 50, 51 & 288.

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