Delay locked loop control circuit

Details Delay locked loop control circuit Delay locked loop control circuit

2005-10-11

2005-10-11

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S222000, C365S233100

Reexamination Certificate

active

06954388

ABSTRACT:
A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.

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