Delay locked loop circuits and methods of operation thereof

Details Delay locked loop circuits and methods of operation thereof Delay locked loop circuits and methods of operation thereof

1999-07-23

2001-09-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S003000

Reexamination Certificate

active

06285225

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to apparatus and methods for synchronizing clock signals in integrated circuit devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices such as microprocessors and peripheral circuits typically operate in a synchronized fashion at very high speeds. For example, in systems including several kinds of integrated circuit devices, each device commonly operates in synchronization with a clock signal provided to the device. Thus, such a system often includes one or more circuits for generating clock signals synchronized to a reference clock signal, such as a phase-locked loop (PLL) circuit that generates an output clock signal having the same phase as an input reference clock signal using a voltage controlled oscillator.
In some applications, however, the use of such PLL circuits may be disadvantageous, as lags associated with control of the voltage controlled oscillator may cause such a PLL circuit to take a significant time to generate an output clock signal having the same phase as the reference clock signal. These control lags may also result in undesirably high power consumption.
The use of delay locked loop (DLL) circuits has been proposed to avoid such problems. A typically DLL circuit generates a delayed clock signal from a reference clock signal, with the delayed clock signal typically being used as a reference signal for operation of devices. A typically DLL circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal.
Conventional DLL circuits typically use a phase comparator similar to that used in PLL circuits. However, using such a phase comparator may be disadvantageous for operation of a DLL circuit. The output clock signal produced by a PLL typically is not a signal delayed from a reference clock signal, but rather a signal produced by a voltage controlled oscillator. Consequently, at arbitrary times, the output clock signal produced by the voltage controlled oscillator of a PLL may be synchronous with a pulse of a reference clock signal.
In contrast, the DLL delays an input reference clock signal to generate a delay clock signal, which generally imposes causality constraints on the operation of the phase comparator. For example, a DLL circuit may malfunction if its phase comparator attempts to synchronize a kth pulse of the reference clock signal with a corresponding pulse of the delayed clock signal produced from the kth pulse of the reference clock signal, as the delay circuit of the DLL generally cannot sufficiently advance the delayed clock signal to provide synchronization.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide delay locked loop circuits which may provide improved performance and methods of operation therefor.
It is another object of the present invention to provide phase comparator circuits for use in delay locked loops which may provide improved performance.
These and other objects, features and advantages are provided, according to embodiments of the present invention, by delay locked loop circuits in which a delayed clock signal is produced from an input clock signal by a variable delay circuit that varies the delay of the delayed clock signal responsive to a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge. In embodiments of the present invention, a delay locked loop circuit includes a phase comparator circuit that asserts first and second phase comparison signals depending on whether an edge of the delayed clock signal corresponding to a first edge of the input clock signal leads or lags a second edge of the input clock signal that follows the first edge of the input clock signal.
In particular, according to an embodiment of the present invention, a delay locked loop circuit includes a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal responsive to a delay control signal applied to the variable delay circuit. A delay control circuit is responsive to the input clock signal and to the delayed clock signal, and applies a delay control signal to the variable delay circuit based on a comparison of a transition of the delayed clock signal corresponding to a first transition of the input clock signal to a second transition of the input clock signal that follows the first transition of the input clock signal. In preferred embodiments, the delay control circuit generates the delay control signal based on a comparison of an edge of the delayed clock signal corresponding to a first edge of the input clock signal to a second edge of the input clock signal that follows the first edge of the input clock signal.
In an embodiment of the present invention, the delay control circuit includes a phase comparator circuit that receives an input clock signal and a delayed clock signal produced therefrom, and produces a phase comparison signal that indicates whether the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads or lags the second edge of the input clock signal. A delay control signal generating circuit applies a delay control signal to the variable delay circuit responsive to the phase comparison signal.
Preferably, the phase comparator circuit asserts a first phase comparison signal if the edge of the delayed clock signal corresponding to the first edge of the input clock signal lags the second edge of the input clock signal, and asserts a second phase comparison signal if the edge of the delayed clock signal corresponding to the first edge of the input clock signal leads the second edge of the input clock signal. The delay control signal generating circuit may generate the delay control signal responsive to the first and second phase comparison signals.
According to another embodiment of the present invention, the delay control signal generating circuit includes a charge pump that generates a delay control signal responsive to at least one phase comparison signal. In one embodiment of the present invention, the charge pump includes a capacitor, a current source, and a current sink. A first switch is operative to couple the current source to the capacitor when a first one of first and second phase comparison signals is asserted. A second switch is operative to couple the current sink to the capacitor when an edge of the input clock signal lags the second edge of the input clock signal.
According to another embodiment of the present invention, the phase comparator circuit includes a first flip-flop having a data input, a clock input, a reset input and an output. The first flip-flop receives the input clock signal at the clock input and a first data signal at the data input, clocking the first data signal to produce a second data signal at the output responsive to an edge of the input clock signal and resetting the second data signal responsive to an initialization signal at the reset input. A second flip-flop having a clock input, a data input, a reset input and an output receives the delayed clock signal at the clock input and the first data signal at the input. The second flip-flop clocks the first data signal to produce the second phase comparison signal at the output of the second flip-flop responsive to an edge of the delayed clock signal, and resets the second phase comparison signal responsive to a reset signal at the reset input. A third flip-flop having a clock input, a data input connected to the output of the first flip-flop, a reset input, and an output, clocks the second data signal to produce the first phase comparison signal at the output of the third flip-flop responsive to an edge of the input clock

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