Delay locked loop circuits and methods of generating clock...

Details Delay locked loop circuits and methods of generating clock... Delay locked loop circuits and methods of generating clock...

2007-06-12

2009-11-24

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S149000, C327S150000, C327S152000, C327S153000, C327S159000

Reexamination Certificate

active

07622971

ABSTRACT:
A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.

REFERENCES:
patent: 2002/0070409 (2002-06-01), Yonemaru
patent: 2007/0024335 (2007-02-01), Sato
patent: 1020030014790 (2003-02-01), None
patent: 1020030062480 (2003-07-01), None
patent: 1020040093819 (2004-09-01), None

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