Delay locked loop circuits and method for controlling the same

Details Delay locked loop circuits and method for controlling the same Delay locked loop circuits and method for controlling the same

2008-01-04

2010-10-12

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

07812654

ABSTRACT:
A delay locked loop circuit and a method for controlling the same including a delay locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal includes at least two delay chains having different types of delay cells for delaying the external clock signal. Thus, the layout area and power consumption can be reduced, and logic failures can be prevented or minimized by replacement or compensation of the main delay cells.

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patent: 2008/0100356 (2008-05-01), Lee

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