Delay locked loop circuitry for clock delay adjustment

Details Delay locked loop circuitry for clock delay adjustment Delay locked loop circuitry for clock delay adjustment

2007-12-11

2007-12-11

Kim, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S149000, C327S158000

Reexamination Certificate

active

11406557

ABSTRACT:
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

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