Delay locked loop circuit of semiconductor device

Details Delay locked loop circuit of semiconductor device Delay locked loop circuit of semiconductor device

2011-08-02

2011-08-02

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S189070, C365S189090

Reexamination Certificate

active

07990785

ABSTRACT:
A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

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