Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-05-07
2002-10-01
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000
Reexamination Certificate
active
06459314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit having a duty cycle correction function and a delay locked method.
2. Description of the Related Art
A delay locked loop circuit, widely deployed in semiconductor devices, receives an external clock signal and generates an internal clock signal for synchronizing signals within the semiconductor device. The internal clock signal is generated to precede the external clock signal by a predetermined time period.
FIG. 1
is a block diagram of a conventional delay locked loop circuit and a conventional duty cycle corrector. Referring to
FIG. 1
, the duty cycle corrector
111
and delay locked loop circuit
121
are serially connected to each other. The duty cycle corrector
111
corrects the duty cycle of the external clock signal (Clk_ext). The delay locked loop circuit
121
receives a clock signal (Clk_dcc), in which the duty cycle is corrected, and generates the internal clock signal (Clk_int), whose phase leads the phase of the external clock signal (Clk_ext). Jitter, or phase noise, always exists in the clock signal (Clk_dcc) output from the duty cycle corrector
111
. The delay locked loop circuit
121
likewise generates jitter. Jitter obtained by adding the jitter generated by the duty cycle corrector
111
to the jitter generated by the delay locked loop circuit
121
exists in the internal clock signal (Clk_int) output from the delay locked loop circuit
121
.
The delay locked loop circuit
121
requires a first locking time for making the phase of the received clock signal (Clk_dcc) the same as the phase of the output internal clock signal (Clk_int). The duty cycle corrector
111
also requires a second locking time for making the phase of the received external clock signal (Clk_ext) the same as the phase of the output clock signal (Clk_dcc). Therefore, the overall system locking time is the sum of the first and second locking times in the case where the duty cycle corrector
111
and the delay locked loop
121
are serially connected.
SUMMARY OF THE INVENTION
To address the above limitations, it is an object of the present invention to provide a delay locked loop circuit, in which jitter and locking time are reduced.
It is another object of the present invention to provide a delay locked method, which is capable of reducing the jitter and locking time.
To achieve the first object, according to an aspect of the present invention, there is provided a delay locked loop circuit, comprising a delaying portion for generating a first output signal by uniformly delaying an input first clock signal and generating a second output signal by variably delaying the first clock signal and an output signal generator for generating a second clock signal, the voltage level of which increases when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state.
It is preferable that the delay locked loop circuit further comprises an integrator for integrating the second clock signal and that the delaying portion generates the second output signal by variably delaying the first clock signal in response to the output signal of the integrator.
The delaying portion preferably comprises a first delay for delaying the first clock signal and generating the first output signal and a second delay for generating the second output signal by variably delaying the first clock signal.
The output signal generator preferably comprises a first pulse signal generator for generating a first pulse signal when the first output signal is transitioned from the first logic state to the second logic state, a second pulse signal generator for generating a second pulse signal when the second output signal is transitioned from the second logic state to the first logic state, and a flip-flop for generating the second clock signal, whose voltage level is increased when the first pulse signal is generated and whose voltage level is reduced when the second pulse signal is generated.
According to another aspect of the present invention, there is provided a delay locked loop circuit, comprising a delaying portion for generating first and second output signals by delaying an input first clock signal by a predetermined time and selectively varying the output time of the first and second output signals and an output signal generator for generating a second clock signal, the voltage level of which is increased when the first output signal is transitioned from a first logic state to a second logic state and the voltage level of which is reduced when the second output signal is transitioned from the second logic state to the first logic state.
It is preferable that the delay locked loop circuit further comprises an integrator for integrating the second clock signal and that the delaying portion variably delays the first clock signal in response to the output signal of the integrator.
The delaying portion preferably comprises a first multiplexer for receiving a reference voltage and a control signal and outputting either the reference voltage or the control signal in response to a selection signal, a first delay for generating a first output signal by controlling the delay time of an input first clock signal in response to the output of the first multiplexer, a second multiplexer for receiving the reference voltage and the control signal and outputting either the reference voltage or the control signal, and a second delay for generating a second output signal by controlling the delay time of the first clock signal in response to the output of the second multiplexer.
It is preferable that the first delay uniformly delays the first clock signal when the first multiplexer outputs the reference voltage and variably delays the first clock signal when the second multiplexer outputs the control signal.
To achieve the second object, according to an aspect of the present invention, there is provided a delay locking method, comprising the steps of receiving a first clock signal, generating a first output signal by uniformly delaying the first clock signal, transitioning a second clock signal from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state, and transitioning the second clock signal from the logic “high” level to the logic “low” level when the second output signal is transitioned from the second logic state to the first logic state.
It is preferable that the step of generating the second output signal further comprises the step of integrating the second clock signal and that the output time of the second output signal varies in response to a signal generated by integrating the second clock signal.
According to another aspect of the present invention, there is provided a delay locking method, comprising the steps of receiving a first clock signal, generating a first output signal by delaying the first clock signal for a first predetermined time, generating a second output signal by delaying the first clock signal for a second predetermined time, transitioning a second clock signal from a logic “low” level to a logic “high” level when the first output signal is transitioned from a first logic state to a second logic state, and transitioning the second clock signal from the logic “high” level to the logic “low” level when a second output signal is transitioned from the second logic state to the first logic state, wherein the output time of the second output signal is variable when the output time of the first output signal is uniform and the output time of the second output signal is uniform when the output time of the first output signal is variable.
It is preferable that each of the steps of generating the first and second output signals further comprises the step of integrating the second clock signal and that the o
Cox Cassandra
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Wells Kenneth B.
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