Delay locked-loop circuit for reducing load of variable...

Details Delay locked-loop circuit for reducing load of variable... Delay locked-loop circuit for reducing load of variable...

2005-09-27

2005-09-27

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C331S025000

Reexamination Certificate

active

06950488

ABSTRACT:
Disclosed is a delay locked-loop circuit comprising a phase detector for detecting a phase difference between an external clock signal and an internal clock signal, a delay unit controller for generating a control signal in response to output of the phase detector, and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising a first group of delay cells used at or above a predetermined frequency, a second group of delay cells used with the first group of delay cells at or below a predetermined frequency, switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal, and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.

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