Delay locked loop circuit for internally correcting duty...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S375000, C375S376000, C327S158000

Reexamination Certificate

active

10619821

ABSTRACT:
A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.

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English translation of abstract for Japanese Patent No. JP1081523.

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