Delay locked loop circuit for controlling delay time with reduce

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375362, 375376, 327161, H03D 324

Patent

active

061447137

ABSTRACT:
A phase comparator is adapted to output a predetermined number of pulse signals corresponding to the phase difference between a comparison reference signal and a comparison object signal to be compared therewith. This phase comparator is applied to a DLL (Delay Locked Loop) circuit having a delay circuit, a dummy delay circuit and a delay controller. Further, the phase comparator has a phase comparing section and a pulse number control section. The phase comparing section is used to make a judgement by comparing the phase difference between the comparison reference signal and the comparison object signal with a predetermined value, and the pulse number control section is used to control a number of pulses to be output according to a result of the judgement made by the phase comparing section. Thereby, when the phase difference between an external clock signal and an internal clock signal (namely, a comparison object signal and a comparison reference signal) at power-up and so forth is large, a quantity of delay which is corrected at a time can be increased. Consequently, the lock-up time of the DLL circuit can be reduced.

REFERENCES:
patent: 4468709 (1984-08-01), Kenjyo
patent: 4598257 (1986-07-01), Southard
patent: 5036297 (1991-07-01), Nakamura
patent: 5041836 (1991-08-01), Paschen et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5635875 (1997-06-01), Kusakabe
patent: 5715286 (1998-02-01), Itoh et al.
patent: 5870002 (1999-02-01), Ghaderi et al.
"A 256 Mb SDRAM Using a Register-Controlled Digital DLL", by Hatakeyama et al., 1997 Digest of Technical Papers and Slide Supplement, Feb. 1977.

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