Delay locked loop circuit and semiconductor memory device...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S175000

Reexamination Certificate

active

08063680

ABSTRACT:
A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.

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patent: 7015739 (2006-03-01), Lee et al.
patent: 7199634 (2007-04-01), Cho et al.
patent: 7528668 (2009-05-01), Kim et al.
patent: 7567106 (2009-07-01), Park et al.
patent: 7825711 (2010-11-01), Ma
patent: 2003/0052719 (2003-03-01), Na
patent: 2007/0152723 (2007-07-01), Ahn et al.
patent: 2000-306399 (2000-11-01), None
patent: 1020080038502 (2008-05-01), None
patent: 1020080074667 (2008-08-01), None

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