Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-11-16
2002-04-02
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S254000, C327S355000
Reexamination Certificate
active
06366148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a delay locked loop circuit for generating an internal clock signal to be used for integrated circuits in semiconductor devices.
2. Description of the Related Art
Delay locked loop (DLL) circuits are used to provide an internal clock signal whose phase is advanced by a predetermined time period ahead of a reference clock signal. Generally, an internal clock signal having a known phase relationship to an external reference clock is required to synchronize semiconductor integrated circuits having a relatively high integration density, such as a Rambus DRAM (RDRAM) and a synchronous DRAM (SDRAM).
Specifically, an external clock reference signal received via an input pin of an integrated circuit device is applied to a clock buffer to generate an internal clock signal. The internal clock signal in turn controls a data output buffer to output data from the integrated circuit device. In this process of outputting data, the internal clock signal is delayed for a certain time period with respect to the external clock signal, and the output of data from the data output buffer is also delayed for a certain time period with respect to the internal clock signal.
Thus, the output of data from the data output buffer is delayed for a longer time period with respect to the external clock signal. In other words, a time period from the input of an external clock signal to the output of data from the output data buffer, which is an output data access time tAC, is lengthened.
To solve such delay problems, there have been provided delay locked loop circuits designed to make the phase of an internal clock signal lead by a predetermined time period, so that data can be output without delay from an external clock signal. That is, in a conventional delay locked loop circuit, when receiving an external clock signal and generating an internal clock signal, the phase of the internal clock signal leads that of the external clock signal by a predetermined time period. Then, the internal clock signal is used as a clock signal for each unit such as a data output buffer.
FIG. 1
is a block diagram of a conventional delay locked loop circuit. A conventional delay locked loop circuit typically includes a phase detector
11
, a charge pump
13
, a voltage controlled delay line (VCDL)
15
and a compensation delay
17
.
In the conventional delay locked loop circuit, a variation width of delay time of the VCDL
15
must be increased to widen an operational frequency band. This is achieved by increasing the variation width of delay time of each unit delay means constituting the VCDL
15
or by separately installing a coarse VCDL and a fine VCDL. However, in the former method to increase the variation width of delay time, variation in the entire delay time with respect to noises of the output of the charge pump
13
, that is, a control voltage Vcon, increases. As a result, jitter may occur in operation signals. In the latter method, jitter may occur as much as corresponding to a coarse unit delay time at the moment that delay time value of the coarse VCDL changes.
To solve the problems in such conventional delay locked loop circuits, delay locked loop circuits using phase interpolation techniques as shown in
FIG. 2
have been developed. Referring to
FIG. 2
, a conventional delay locked loop circuit using the phase interpolation techniques includes a phase detector
21
, a charge pump
22
, a phase interpolator
23
, a compensation delay unit
24
, a phase splitter
25
, a phase selector
26
and a control circuit
27
.
While such conventional delay locked loop circuits using the phase interpolation techniques can prevent occurrence of jitter, size of a chip using such a delay locked loop circuit increases, when it is realized as a semiconductor integrated circuit, due to the phase detector
25
, the phase selector
26
and the control circuit
27
necessary to prevent jitter.
Therefore, a need exists for a delay locked loop circuit which prevents the occurrence of jitter and requires a small area when being fabricated as an integrated circuit in a semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a delay locked loop circuit which can prevent occurrence of jitter and has a small area when it is realized as a semiconductor integrated circuit.
Another object of the present invention is to provide a method of generating an internal clock signal to be used for integrated circuits in semiconductor devices, where the method prevents occurrence of jitter in the integrated circuits.
According to an aspect of the present invention to achieve the first object, there is provided a delay locked loop circuit for receiving an input clock signal (i.e., an external clock signal) and generating an output clock signal (i.e., an internal clock signal), the phase of which leads that of the input clock signal by a predetermined time. The delay locked loop circuit includes a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal, the phase of which lags that of the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the phase of the second component coefficient; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the inverted second component coefficient by the second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
According to another aspect of the present invention to achieve the first object, there is provided a delay locked loop circuit for receiving an input clock signal and generating an output clock signal, the phase of which leads that of the input clock signal by a predetermined time. The delay locked loop circuit includes a phase shifter for generating a first clock signal in phase with the input clock signal and a second clock signal having a 90° phase difference with respect to the first clock signal; a compensation delay unit for outputting a third clock signal, the phase of which lags that of the input clock signal by the predetermined time; a component coefficient extractor for extracting a first component coefficient of the third clock signal with respect to the first clock signal and a second component coefficient of the third clock signal with respect to the second clock signal; a phase inverter for inverting the phase of the second clock signal; a first component signal generator for generating a first component signal by multiplying the first component coefficient by the first clock signal; a second component signal generator for generating a second component signal by multiplying the second component coefficient by the inverted second clock signal; and a phase mixer for mixing the first and second component signals to generate the output clock signal.
Preferably, the component coefficient extractor includes: a first multiplier for multiplying the first clock signal by the third clock signal; a second multiplier for multiplying the second clock signal by the third clock signal; a first low pass filter for low-pass filtering the output signal of the first multiplier to output the first component coefficient; and a second low pass filter for low-pass filtering the output signal of the second multiplier to output the second component coefficient.
Alternatively, the component coefficient extractor can includes: a phase detector for rec
Cox Cassandra
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
Tran Toan
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