Delay locked loop capable of compensating for delay of...

Details Delay locked loop capable of compensating for delay of... Delay locked loop capable of compensating for delay of...

2006-06-27

2006-06-27

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000

Reexamination Certificate

active

07068084

ABSTRACT:
In a delay locked loop (DLL) of a semiconductor memory device capable of compensating for delay of an internal clock signal by variation of driving strength of an output driver, a replica output driver exhibits the same delay amount as the delay amount as an output driver whose driving strength varies. A phase detector detects a phase difference between an internal clock signal which is delayed by the replica output driver, and an external clock signal. A control circuit generates a control signal in response to the output signal of the phase detector. A variable delay circuit, in response to the control signal, delays the external clock signal and generates the internal clock signal in synchronization with the external clock signal. Since the DLL has a replica output driver which can accurately track the delay of an internal clock signal by variation of the driving strength of an output driver in the feedback loop, output data can be accurately synchronized with an external clock signal.

REFERENCES:
patent: 5973525 (1999-10-01), Fujii
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 6476653 (2002-11-01), Matsuzaki
patent: 6493829 (2002-12-01), Kubo
patent: 6509776 (2003-01-01), Kobayashi et al.
patent: 6720807 (2004-04-01), Kubo et al.
patent: 2000-59210 (2000-02-01), None
patent: 2002-0059229 (2002-07-01), None

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