Delay locked loop and semiconductor memory device with the same

Details Delay locked loop and semiconductor memory device with the same Delay locked loop and semiconductor memory device with the same

2009-11-10

2011-11-08

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S233100, C365S233120, C327S156000, C327S158000, C327S296000

Reexamination Certificate

active

08054701

ABSTRACT:
A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.

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Notice of Allowance issued from Korean Intellectual Property Office on Feb. 7, 2011.
Lee et al., “Design of CMOS Analog/Mixed-Mode Integrated System vol. 2”, Sigma Press, 1999, pp. 307-308, 311, 330-331, South Korea.
Examiner's Answer to Appeal Brief as filed with the Patent Court of Korea: Jan. 13, 2010.

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