Delay locked loop and semiconductor memory device having the...

Details Delay locked loop and semiconductor memory device having the... Delay locked loop and semiconductor memory device having the...

2007-04-10

2007-04-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S161000

Reexamination Certificate

active

11265945

ABSTRACT:
In a delay locked loop and a semiconductor memory device having the same, the delay locked loop includes a phase detecting and control signal generator for detecting a phase difference between a clock signal and a feedback clock signal and generating a plural-bit delay control signal which varies according to the phase difference; a first delay having a predetermined number of first delay cells which are cascade-connected for delaying the clock signal to generate a plurality of output clock signals and the feedback clock signal in response to the plural-bit delay control signal; a second delay having a predetermined number of second delay cells which are cascade-connected for delaying an inverted clock signal to generate a plurality of inverted output clock signals in response to the plural-bit delay control signal; and a phase mixer for phase-mixing corresponding clock signals among the plurality of output clock signals and the plurality of inverted output clock signals to output a plurality of corrected output clock signals.

REFERENCES:
patent: 6340910 (2002-01-01), Saeki
patent: 6680635 (2004-01-01), Lee
patent: 6768361 (2004-07-01), Kwak
patent: 6911853 (2005-06-01), Kizer et al.
patent: 2004/0080349 (2004-04-01), Kawahito et al.
patent: 2005/0093600 (2005-05-01), Kwak
patent: 2001-007686 (2001-01-01), None
patent: 10-2004-0044219 (2004-05-01), None

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