Delay locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Reexamination Certificate

active

07868671

ABSTRACT:
A delay locked loop may include a period locked loop portion. The period locked loop portion may include a delay. The delay may include an even number of delay cells dependently connected in the form of a ring configured to generate an even number of delay clock signals. Transition of at least one delay clock signal of the even number of delay clock signals is configured to be controlled in response to an activated one first selecting signal of an even number of first selecting signals, and transition of the remaining clock signals is configured to occur in response to the at least one delay clock signal.

REFERENCES:
patent: 6255880 (2001-07-01), Nguyen
patent: 7046059 (2006-05-01), Kwak
patent: 7057431 (2006-06-01), Kwak
patent: 7088159 (2006-08-01), Kwak et al.
patent: 7142026 (2006-11-01), Kwak
patent: 7161397 (2007-01-01), Lee et al.
patent: 7358784 (2008-04-01), Kim et al.
patent: 2005/0007166 (2005-01-01), Shin
patent: 10-2001-0011503 (2001-02-01), None
patent: 10-2002-0011503 (2001-02-01), None
patent: 10-2004-0064862 (2004-07-01), None
patent: 10-2005-0048838 (2005-05-01), None
patent: 10-2005-0058918 (2005-06-01), None
patent: 10-2006-0041117 (2006-05-01), None
Korean Decision of Grant dated Jul. 28, 2008 in the corresponding Korean Patent Application No. 10-2006-0062110.

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