Delay locked loop

Details Delay locked loop Delay locked loop

2006-04-28

2009-06-30

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S270000, C327S271000, C327S272000

Reexamination Certificate

active

07554371

ABSTRACT:
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

REFERENCES:
patent: 6982579 (2006-01-01), Lee
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patent: 10-2004-0046325 (2004-06-01), None
Korea Office Action dated Aug. 31, 2006.
German Office Action dated Mar. 3, 2008.

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