Delay locked loop

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S371000, C375S373000, C327S149000, C327S150000, C327S153000, C327S156000, C327S158000, C327S159000, C327S161000

Reexamination Certificate

active

07457392

ABSTRACT:
A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

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Shigehiro Kuge et al.: “A 0.18 μm 256Mb DDR-SDRAM with Low-Cost Post-Mold-Tuning Method for DLL Replica”,2000 IEEE International Solid-State Circuits Conference, 4 pgs., Order No. 07803-5853-8/00.

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