Delay/load estimation for use in integrated circuit design

Details Delay/load estimation for use in integrated circuit design Delay/load estimation for use in integrated circuit design

2000-12-12

2003-10-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06634014

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns estimation of delays and electrical loads during integrated circuit (IC) design, particularly during the early phases of IC design.
2. Description of the Prior Art
Integrated circuit design typically includes the following steps performed in the following order: (i) designing the circuit in a hardware description language (HDL), often including register transfer level (RTL) descriptions; (ii) RTL floor planning, bus planning and global interconnect planning; (iii) delay and load estimation; and then (iv) synthesis of the HDL to provide a netlist description of the circuit. In conventional integrated circuit design, delay and load estimation in step (iii) often are performed by simply considering the number and type of receiving elements for a particular driving element, estimating wire length required for interconnections, and using expected technology-dependent values for the capacitances-per-unit-length and resistances-per-unit-length for such interconnections.
The present inventors have discovered, however, that this conventional technique for estimating delay and load prior to synthesis often is insufficiently accurate, frequently leading to inappropriate design choices early on in the design process.
SUMMARY OF THE INVENTION
The present invention addresses this problem by providing a technique in which delays and/or loads are estimated in an IC design, based on HDL floor planning, but by first inserting buffers into the IC design in anticipation of processing to be performed later in the IC design process.
Thus, in one aspect the invention is directed to performing delay estimation prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays are estimated in the IC design while taking into account the effect of the inserted buffers. It is a feature of this aspect of the invention that the buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.
In another aspect, the invention is directed to performing load estimation prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, loads are estimated in the IC design while taking into account the effect of the inserted buffers. It is a feature of this aspect of the invention that the buffers are inserted in-the foregoing processing based on anticipated processing later in the IC design process.
By inserting buffers into an IC description, prior to performing load or delay estimation in the foregoing manners and in anticipation of processing later in the IC design process, the present invention often can provide more accurate delay and/or load estimates than conventional techniques would permit. As a result, more appropriate design choices often can be made (such as during the synthesis phase), thereby frequently reducing the number of subsequent design problems and shortening the overall design process.
In a more particular aspect of the invention, the buffers are inserted according to rules that are similar to predetermined rules used in inserting buffers later on in the design process based on physical layout. As a result, a better estimate of what the final loads and/or delays will be often can be obtained early on in the design process.


REFERENCES:
patent: 5544071 (1996-08-01), Keren et al.
patent: 6145117 (2000-11-01), Eng
patent: 6216252 (2001-04-01), Dangelo et al.

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