Delay line and memory control circuit utilizing the delay line

Details Delay line and memory control circuit utilizing the delay line Delay line and memory control circuit utilizing the delay line

2011-03-22

2011-03-22

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S230080

Reexamination Certificate

active

07911859

ABSTRACT:
A delay line includes at least one delay cell, wherein the delay line utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor. In addition, a memory control circuit includes a delay locked loop (DLL) having at least one delay cell. The delay locked loop utilizes at least one of the at least one delay cell to delay an input signal for generating an output signal, and the at least one delay cell is implemented by a Pseudo NMOS transistor.

REFERENCES:
patent: 6756853 (2004-06-01), Schmitt et al.
patent: 7694202 (2010-04-01), Swanson et al.
patent: 7724862 (2010-05-01), Menolfi et al.
patent: 2003/0227333 (2003-12-01), Schmitt et al.

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