Delay estimation using edge specific miller capacitances

Details Delay estimation using edge specific miller capacitances Delay estimation using edge specific miller capacitances

2006-05-23

2006-05-23

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C324S628000, C324S677000

Reexamination Certificate

active

07051305

ABSTRACT:
A method of estimating delay which includes configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge, and using the Miller factors to perform a timing analysis.

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