Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-31
2006-10-31
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07131082
ABSTRACT:
Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.
REFERENCES:
patent: 5365463 (1994-11-01), Donath et al.
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 5636372 (1997-06-01), Hathaway et al.
patent: 5638290 (1997-06-01), Ginetti et al.
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5768130 (1998-06-01), Lai
patent: 5847966 (1998-12-01), Uchino et al.
patent: 6304836 (2001-10-01), Krivokapic et al.
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6714902 (2004-03-01), Chao et al.
patent: 2001/0020289 (2001-09-01), Pavisic et al.
patent: 04-211872 (1992-08-01), None
patent: 07-013974 (1995-01-01), None
patent: 07-254009 (1995-10-01), None
patent: 08-129568 (1996-05-01), None
patent: 09-198419 (1997-07-01), None
patent: 11-039357 (1999-02-01), None
Tsukiyama, Shuji., et al. “On a Technique to Eliminate False-Paths for the Statistical Static Timing Analysis.” Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, vol. 100, No. 534, (VLD2000-121), Jan. 12, 2001, pp. 33-40.
Nishimura, Shuji., et al. “A Statistical Static Timing Analyzer for CMOS Combinatorial Circuits Considering Correlations Between Delays.” Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, vol. 100, No. 475, (VLD2000-71), Nov. 23, 2000, pp. 11-16.
Tsukiyama, Shuji., et al. “An Estimation Algorithm of the Critical Path Delay for a Combinatorial Circuit.” The 13th Workshop on Circuits and Systems in Karuizawa, Apr. 24-25, 2000, pp. 131-136, (w/English Translation).
U.S. Appl. No. 09/793,564, filed Feb. 27, 2001, Tanaka et al.
Shuji Nishimoto et al., “A Performance Test of the Statistical Static Timing Analyzer Considering Correlations Between Delays”, The Institute of Electronics, Information and Communication Engineers, Mar. 2001, (Partial English Translation therof).
B. Choi et al., “Timing Analysis of Combinatorial Circuits Including Capacitive Coupling and Statistical Process Variation”, VLSI Test Symposium. 2000, Proceedings, IEEE, Apr. 30, 2000-May 4, 2000, pp. 49-54.
S. Tongsima et al., “Optimizing Circuits with Confidence Probability using Probabalistic Retiming”, Circuits and Systems, 1998, ISCAS '98, Proceedings, IEEE International Symposium, May 31, 1998-Jun. 3, 1998, pp. 270-273.
H.F. Jyu et al., “Statistical Timing Analysis of Combinatorial Logic Circuits”, IEEE Trans. VLSI Systems, vol. 1, No. 2, pp. 126-137, 1993.
Tsukiyama, Shuji, et al. “On a Technique to Eliminate False-Paths for the Statistical Static Timing Analysis.” Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, vol. 100, No. 534, (VLD2000-121), Jan. 12, 2001, pp. 33-40.
Nishimura, Shuji., et al. “A Statistical Static Timing Analyzer for CMOS Combinatorial Circuits Considering Correlations Between Delays.” Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, vol. 100, No. 475, (VLD2000-71), Nov. 23, 2000, pp. 11-16.
Tsukiyama, Shuji., et al. “An Estimation Algorithm of the Critical Path Delay for a Combinatorial Circuit.” The 13th Workshop on Circuits and Systems in Karuizawa, Apr. 24-25, 2000, pp. 131-136, (w/English Translation).
Fukui Masahiro
Tanaka Masakazu
Tsukiyama Shuji
Dinh Paul
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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