Delay diagnosis method for semiconductor integrated circuit,...

Details Delay diagnosis method for semiconductor integrated circuit,... Delay diagnosis method for semiconductor integrated circuit,...

2006-03-14

2006-03-14

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07013443

ABSTRACT:
A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic information and floor plan information, finding the number of start points connected to the end point of a path from the logic information, computing the logic stage number of the path from the number of start points, finding block-to-block distances from the floor plan information, computing intra-block delays from the logic stage number and gate unit-value delays, computing inter-block delays from the block-to-block distances and routing unit-value delays, and diagnosing if the delay of the path after logic synthesis can be converged within a target path delay from the relation among the computed intra-block delays and inter-block delays and the target path delay.

REFERENCES:
patent: 2005/0107970 (2005-05-01), Franch et al.
patent: 2888708 (1999-02-01), None
patent: 11-282896 (1999-10-01), None
patent: 2001-148425 (2001-05-01), None
patent: 2001-160078 (2001-06-01), None

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