Delay clock generating apparatus and delay time measuring...

Details Delay clock generating apparatus and delay time measuring... Delay clock generating apparatus and delay time measuring...

2003-04-23

2004-10-19

Bayard, Emmanuel (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C327S152000, C327S161000

Reexamination Certificate

active

06807243

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay clock generating apparatus which generates a delay clock, and more particularly to a delay clock generating apparatus which is incorporated in a delay signal generator of a semiconductor testing device, which tests a semiconductor device.
2. Description of the Related Art
Recently, it has been necessary for a semiconductor testing device for testing a semiconductor device to control extremely high-speed operational timings, due to developments of semiconductor devices which operate at high-speed. It has been especially necessary that the semiconductor testing device delay timing with respect to a standard clock, for inputting a test pattern to a device under test (DUT), by an accurate delay time, in accordance with an input characteristic of the DUT.
FIG. 1
is a block diagram showing a delay line
176
in the semiconductor testing device, generating a delay indicator signal which is delayed by a predetermined time. The delay line
176
includes delay elements
180
,
184
,
188
and
192
, selectors
182
,
186
,
190
and
194
, and a memory
196
. In this delay line
176
, a clock is input to an input terminal and the delay indicator signal, which is delayed by a predetermined time with respect to the input clock, is output from an output terminal.
The memory
196
stores data in predetermined addresses, of combinations of the delay elements generating a predetermined delay time. Each of the selectors
182
,
186
,
190
and
194
selects either of the clocks, one of which is passed through each of the delay elements
180
,
184
,
188
and
192
and the other of which is not passed through each of the delay elements
180
,
184
,
188
and
192
, and outputs the selected clock. For example, when the delay element
182
uses the delay element
180
in order to generate a predetermined delay time, “0” is stored in the corresponding bit of the memory
196
. When, on the other hand, the delay element
182
does not use the delay element
180
in order to generated the predetermined delay time, “1” is stored in the corresponding bit of the memory
196
.
Each of the delay elements
180
,
184
,
188
and
192
in the delay line
176
are set to have delay times of about several picoseconds, several tens of picoseconds, or several hundred picoseconds. Therefore, logically, three delay elements respectively having delay times of 10 picoseconds, 20 picoseconds, and 40 picoseconds should be provided, in order to set seven delay times of 10 picoseconds, 20 picoseconds, . . . , 70 picoseconds. The combinations of the three delay elements provide the seven delay times.
However, actually, errors occur between the actual delay time provided by the delay elements and the set delay time, because the quality of the delay elements are not equal, and delay time provided by the delay elements varies depending on the ambient temperature. It is necessary to determine the optimum combination of the delay elements by measuring the delay time provided by the delay times, in order to give a predetermined delay time.
FIG. 2
is a block diagram of a conventional semiconductor testing device in which an output signal output from a waveform formatter
12
, which is delayed with respect to a signal generated by a pattern generator
10
, is measured. In this measurement, the pattern generator
10
supplies a standard clock
34
to a timing generator
14
and supplies a measurement signal
32
to the waveform formatter
12
for measuring the delay time. The timing generator
14
includes a plurality of the delay lines
176
, shown in
FIG. 1
, and generates the delay indicator signal
36
which is delayed by a predetermined time with respect to the standard clock
34
, based on the arbitrarily selected combinations of the delay elements. The delay indicator signal
36
is supplied to the waveform formatter
12
. The waveform formatter
12
delays the measurement signal
32
based on the delay indicator signal
36
and outputs the delayed measurement signal
38
to the oscilloscope
16
. The oscilloscope
16
measures the delay time generated by the arbitrarily selected combinations of the delay elements. The data for the combinations of the delay elements are stored in predetermined addresses of the memory
196
, shown in FIG.
1
.
Conventionally, the delay time generated by the combinations of each of the delay elements is measured by the oscilloscope
16
. The combinations of the delay elements and the corresponding data of the delay times are stored in the memory
196
. The delay elements which can generate a desired delay time are selected based on the data stored in the memory
196
, in accordance with the input characteristic of the semiconductor device when testing the semiconductor device.
Using the conventional method of measuring delay times creates disadvantages, because the delay times are measured by the oscilloscope
16
. The oscilloscope
16
cannot measure waveforms output from the waveform formatter
12
corresponding to a plurality of pins of the waveform formatter
12
. Furthermore, the oscilloscope
16
cannot measure an accurate delay time when the delay time is very small, for example, approximately several picoseconds, or several tens of picoseconds.
Conventionally, it was difficult to measure an accurate delay time generated by a combination of the delay elements, by measuring a delay clock, because it was difficult to generate the delay clock having an accurate delay time.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a delay time measuring apparatus and a method of measuring delay times, capable of accurately measuring delay times of a plurality of parallel set delay lines.
It is an object of the present invention to provide a method of setting a combination of delay clocks that can generate a predetermined delay time.
It is an object of the present invention to provide a delay clock generating apparatus capable of generating a delay clock having an accurate delay time.
It is further an object of the present invention to provide a delay clock generating apparatus and a method of measuring delay times, which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the above-stated problem, the present invention provides a delay clock generating apparatus generating a delay clock which is delayed by a predetermined time with respect to a standard clock, comprising: an oscillator oscillating a shift clock having a same cycle as the standard clock; a pulse inserter generating a pulse to be inserted in a reference shift clock, at least either of an upward shift or a downward shift of the reference shift clock being synchronized with an upward shift or a downward shift of the shift clock, respectively, the pulse inserter inserting the pulse in the reference shift clock; and a phase-lock unit generating the delay clock delayed by the predetermined time with respect to the standard clock, by delaying a phase of the shift clock oscillated by the oscillator with respect to a phase of the standard clock based on a reference standard clock synchronizing the standard clock and having a same cycle as the reference shift clock, and the reference shift clock including the insert-pulse.
The delay clock generating apparatus may further comprise a phase comparator outputting the reference standard clock and the reference shift clock based on a phase difference between a synchronous shift clock synchronizing the shift clock and a synchronous standard clock synchronizing the standard clock and having a same cycle as the synchronous shift clock.
The phase comparator may output the reference standard clock and the reference shift clock such that a downward shift of the reference standard clock and a downward shift of the reference shift clock are matched with each other, based on the

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