Delay circuit with timing adjustment function

Details Delay circuit with timing adjustment function Delay circuit with timing adjustment function

2007-03-27

2007-03-27

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C327S149000, C327S158000, C327S161000

Reexamination Certificate

active

10463537

ABSTRACT:
In a phase locked loop circuit, a phase comparator compares the phase of input clock and that of output clock, and provides a control signal as the comparison result. A charge pump circuit includes a clamp circuit, and based on the control signal, provides a control voltage of which lower limit is the reference voltage level. A voltage controlled oscillator receives the control voltage and a second control voltage from the outside and generates output clock having a frequency in accordance with the control voltages. Each delay stage of a delay section is configured with a plurality of delay units identical to that in the voltage controlled oscillator. The delay stage controls the delay time in response to the supply of the control voltage and the second control voltage.

REFERENCES:
patent: 6166572 (2000-12-01), Yamaoka
patent: 6389090 (2002-05-01), Zortea et al.
patent: 6888386 (2005-05-01), Peng
patent: 7057435 (2006-06-01), Mahanavelu et al.
patent: 8-18414 (1996-01-01), None
patent: 9-8617 (1997-01-01), None
patent: 11-274904 (1999-10-01), None
patent: 2000-31818 (2000-01-01), None
patent: 2000-341099 (2000-12-01), None
patent: 2000-357951 (2000-12-01), None

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