Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-29
2003-07-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06598212
ABSTRACT:
This patent application claims priority based on a Japanese patent application, 2000-259446 filed on Aug. 29, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay circuit, a testing apparatus, and a capacitor. More particularly, the present invention relates to a delay circuit which generates a desired delay time by changing the junction capacitance of a field effect transistor.
2. Description of the Related Art
FIG. 1
shows a conventional delay circuit
300
. The conventional delay circuit
300
has a first buffer
302
which shapes the wave form of an input signal and then outputs the resultant shaped signal, a path
306
through which the output signal transmits, a first capacitor
312
which adds capacitance C to the path
306
, a second capacitor
314
which adds capacitance C′ to the path
306
, a first switching device
308
which electrically connects or disconnects the path
306
with the first capacitor
312
, a second switching device
310
which electrically connects or disconnects the path
306
with the second capacitor
314
, and a second buffer
304
which shapes the wave form of the signal that has transmitted through the path
306
and outputs the resultant shaped signal. A control unit not shown in the drawing controls the switching devices
308
and
310
so as to change the capacitance added to the path
306
. In this way, the control unit not shown in the drawing delays the signal that transmits the path
306
by a desired length of time.
The conventional delay circuit
300
achieves a fine delay resolution by selectively adding either the capacitance C or the capacitance C′ which differs slightly from the capacitance C. However, in the conventional delay circuit
300
, the channel capacitance of the first switching device
308
differs from that of the second switching device
310
, and the wire capacitance of the wire which connects the first capacitor
312
with the path
306
differs from the wire capacitance of the wire which connects the second capacitor
314
with the path
306
. These capacitance differences influence the capacitance added to the path
306
. As a result, the desired fine delay resolution which is designed to be achieved by utilizing the fine difference between the capacitance C and the capacitance C′ has been very difficult.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a delay circuit, a testing apparatus, and a capacitor which overcome the above-described problem. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a delay circuit having a buffer which shapes the wave form of an input signal and outputs a shaped signal, a field effect transistor which has a source region, a drain region, a gate electrode, and a substrate on which the source region and the drain region are installed, and an impressed voltage control unit which impresses a desired voltage to the gate electrode is provided. The source region and the drain region are connected to a path through which an output signal transmits. The desired voltage is then impressed to the gate electrode so as to control the capacitance between the source region, the drain region, and the substrate. In this way, the signal is delayed by a desired length of time.
Moreover, it is preferable that the delay circuit have several field effect transistors connected to the path such that the impressed voltage control unit controls the capacitance added to the path by impressing a desired voltage to the gate electrode of each of the several field effect transistors. It is preferable that the impressed voltage control unit have a digital analog converter. Moreover, the delay circuit may further have a capacitor having a prescribed capacitance connected to the path.
According to the second aspect of the present invention, a testing apparatus which supplies a test signal to an electronic device and tests the electronic device is provided. This testing apparatus has a pattern generating unit which generates a pattern that corresponds to the test signal, a wave form shaping unit having a delay circuit for generating a delay signal that corresponds to the operation characteristic of the electronic device, which shapes the pattern and outputs the test signal, a signal input output unit which supplies the test signal to the electronic device and receives an output signal output from the electronic device, and a judging unit which judges whether the electronic device is acceptable or not based on the output signal. The delay circuit has a buffer which shapes the wave form of an input signal and outputs a shaped signal, a field effect transistor having a source region, a drain region, a gate electrode, and a substrate on which the source region and the drain region are installed, and an impressed voltage control unit which impresses a desired voltage to the gate electrode. The source region and the drain region are connected to a path through which an output signal transmits. The delay signal is generated controlling the capacitance between the source region, the drain region, and the substrate by impressing the desired voltage to the gate electrode.
According to the third aspect of the present invention, a capacitor having a capacitance between a first terminal and a second terminal is provided. This capacitor has a field effect transistor having a source region, a drain region, a gate electrode, and a substrate on which the source region and the drain region are installed, and an impressed voltage control unit which controls the capacitance between the first terminal and the second terminal by impressing one of three or more predetermined voltages to the gate electrode. The source region and the drain region are connected to the first terminal, and the substrate is connected to the second terminal.
This summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the above-described features. The above and other features and advantages of the present invention will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5297056 (1994-03-01), Lee et al.
patent: 6209122 (2001-03-01), Jyu et al.
patent: 69308978 (1997-09-01), None
patent: 10005620 (2001-08-01), None
Advantest Corporation
Dinh Paul
Smith Matthew
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