Delay circuit having a plurality of memory cells and correspondi

Details Delay circuit having a plurality of memory cells and correspondi Delay circuit having a plurality of memory cells and correspondi

1996-02-01

1997-08-26

Callahan, Timothy P.

Static information storage and retrieval

Systems using particular element

Capacitors

365233, 327284, G11C 700, G11C 1124

Patent

active

056616791

ABSTRACT:
A delay circuit having at least two memory cells (3, 4, 5, 6, 8, 9) each including a capacitive memory element (20, 26, 40, 45), a write transistor (22, 28, 42, 47) by which information to be delayed can be written from a write line (18) into the capacitive memory element (20, 26, 40, 45), and a read transistor (21, 27, 41, 46) by which information can be read from the capacitive memory element (20, 26, 40, 45) on a read line (19), and having a control arrangement which is clocked by means of a first control clock and whose input receives a control signal and which includes intercoupled control circuits (11, 12, 13, 14, 15, 16) one of which is associated with a respective memory cell (3, 4, 5, 6, 8, 9), each control circuit (11, 12, 13, 14, 15, 16) of the read transistor (21, 27, 41, 46) of the associated memory cell (3, 4, 5, 6, 8, 9) being controllable by means of the input signal and each control circuit (11, 12, 13, 14, 15, 16) of the write transistor (22, 28, 42, 47) of the associated memory cell being controllable by means of the output signal, in which each control circuit (11, 12, 13, 14, 15, 16) has a first control element (43, 48, 24, 30) and a subsequent second control element (44, 49, 25, 31), those control circuits (14) whose preceding control circuit (11) is arranged locally remote have a third control element (29) preceding the first control element (30), in that the input of the third control element (29) receives the output signal of the first control element (24) of the preceding, spatially remote control circuit (11), and in that the first control elements (43, 48, 24, 30) of the control circuits (11, 12, 13, 14, 15, 16) are clocked by the first clock and the second (44, 49, 25, 31) and third (29) control elements of the control circuits (11, 12, 13, 14, 15, 16) are clocked by a second clock.

REFERENCES:
patent: 5012143 (1991-04-01), Boudewijns
patent: 5068825 (1991-11-01), Mahant-Shetti et al.
patent: 5313438 (1994-05-01), Hieda et al.
patent: 5493527 (1996-02-01), Lo et al.
patent: 5519660 (1996-05-01), Iwahashi
patent: 5544096 (1996-08-01), Takasugi
patent: 5555215 (1996-09-01), Nakagome et al.
patent: 5566116 (1996-10-01), Kang
patent: 5574681 (1996-11-01), Foss et al.
patent: 5574694 (1996-11-01), Van Der Ropp

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