Electronic digital logic circuitry – Interface – Current driving
Patent
1994-06-28
1997-01-28
Westin, Edward P.
Electronic digital logic circuitry
Interface
Current driving
326 33, 327264, 327288, 327290, H03K 190948, H03K 1716
Patent
active
055981119
ABSTRACT:
A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor. The P-channel MOS transistor and the N-channel MOS transistor switch among a first state in which the P-channel MOS transistor operates in a saturation region and the N-channel MOS transistor operates in a cutoff region, a second state in which the P-channel MOS transistor operates in an active region and the N-channel MOS transistor operates in the active region, and a third state in which the P-channel MOS transistor operates in the cutoff region and the N-channel MOS transistor operates in the saturation region.
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Mead et al., Intro to VLSI Systems, Addison-Wesley, 1980, pp. 33-37.
NEC Corporation
Santamauro Jon
Westin Edward P.
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