Delay circuit for digital signal processing

Electronic digital logic circuitry – Interface – Current driving

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Details

326 33, 327264, 327288, 327290, H03K 190948, H03K 1716

Patent

active

055981119

ABSTRACT:
A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor. The P-channel MOS transistor and the N-channel MOS transistor switch among a first state in which the P-channel MOS transistor operates in a saturation region and the N-channel MOS transistor operates in a cutoff region, a second state in which the P-channel MOS transistor operates in an active region and the N-channel MOS transistor operates in the active region, and a third state in which the P-channel MOS transistor operates in the cutoff region and the N-channel MOS transistor operates in the saturation region.

REFERENCES:
patent: 4103188 (1978-07-01), Morton
patent: 4255723 (1981-03-01), Ebihara
patent: 4833473 (1989-05-01), Dingwall
patent: 4837466 (1989-06-01), Kanauchi
patent: 4906871 (1990-03-01), Iida
patent: 5041741 (1991-08-01), Steele
patent: 5051625 (1991-09-01), Ikeda et al.
patent: 5097159 (1992-03-01), Seki et al.
patent: 5303191 (1994-04-01), Eagan et al.
Mead et al., Intro to VLSI Systems, Addison-Wesley, 1980, pp. 33-37.

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