Delay circuit for analog signals

Details Delay circuit for analog signals Delay circuit for analog signals

1999-03-08

2000-05-09

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Signals

365 45, 365149, 365239, G11C 700

Patent

active

060612797

ABSTRACT:
A delay circuit is provided, which is capable of eliminating the influence of noise of low frequency as disturbance. A plurality of memory cells including a plurality of capacitors store an analog signal as an input signal by storing charge of the input signal in the capacitors. A first inverting device inverts the input signal to generate an inverted signal. A control circuit generates and delivers control signals to the memory cells to select the input signal and the inverted signal alternately and sequentially write the selected signals into the memory cells in a predetermined writing sequence. The control circuit further generates and delivers to the memory cells to sequentially read out the input signal and the inverted signal from the memory cells in a sequence corresponding to the predetermined writing sequence. A second inverting device inverts the read-out inverted signal. An output signal is synthesized from the read-out input signal and an output signal of the second inverting device.

REFERENCES:
patent: 5717624 (1998-02-01), Kusumoto et al.
patent: 5793698 (1998-08-01), Komarek et al.
patent: 5798960 (1998-08-01), Hughes

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