Delay circuit and delay chain circuit for measurement of the cha

Details Delay circuit and delay chain circuit for measurement of the cha Delay circuit and delay chain circuit for measurement of the cha

1999-05-06

2000-04-25

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Signals

365149, 327153, G11C 700

Patent

active

06055195&

ABSTRACT:
A delay circuit is provided to dynamic random-access memory (DRAM) for use to assist the measurement of the DRAM charge/discharge period, which allows the DRAM charge/discharge period to be more precisely measured. In measurement, a plurality of such delay circuits are chained together to allow the charge/discharge period measurement to be performed in a collective manner on all the DRAM cells in the delay chain circuit, which can be then used to determine the charge/discharge period of each DRAM cell. When the charge or discharge process on the DRAM cell in the current stage is completed, the DRAM-cell delay circuit of the current stage will likewise generate an output voltage of a certain logic state to trigger the next stage to undergo a charge/discharge process. Furthermore, a large-current output driving circuit is coupled to the last stage in the delay chain circuit to allow an increased output driving capability.

REFERENCES:
patent: 5392251 (1995-02-01), Manning

Affiliated with

Also associated with

Rating

Delay circuit and delay chain circuit for measurement of the cha does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay circuit and delay chain circuit for measurement of the cha, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay circuit and delay chain circuit for measurement of the cha will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-998987