Delay circuit

Details Delay circuit Delay circuit

2005-06-07

2005-06-07

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S093000

Reexamination Certificate

active

06903577

ABSTRACT:
An input signal (SIN) is inverted by an inverter (101), and the inverted input signal is entered into a tri-state type inverter (104). An output portion of this inverter is connected via a delay path (105) to an input portion of an operational amplifier (106). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit (103) controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S11) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S16) output from the operational amplifier. As a result, an amplitude of a signal (S15) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (106), and a delay time is made constant.

REFERENCES:
patent: 5095233 (1992-03-01), Ashby et al.
patent: 5233617 (1993-08-01), Simmons et al.
patent: 5748616 (1998-05-01), Riley
patent: 6747500 (2004-06-01), Mawet
patent: 6765423 (2004-07-01), Higuchi
patent: 6836127 (2004-12-01), Marshall et al.
patent: 6842044 (2005-01-01), Feng et al.

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