Delay and signal integrity check and characterization

Details Delay and signal integrity check and characterization Delay and signal integrity check and characterization

2007-04-10

2007-04-10

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S016000

Reexamination Certificate

active

10981803

ABSTRACT:
A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter. The method of this signal integrity and delay check can be applied to semiconductor IPs (Intellectual Property) including cell, I/O and memory circuit characterization and verification.

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