Delay analysis result display device

Details Delay analysis result display device Delay analysis result display device

1998-10-21

2001-03-20

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06205573

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay analysis result display device and particularly, to a delay analysis result display device for a logic circuit.
2. Description of the Prior Art
FIG. 11
is a general circuit diagram of a logic circuit. This circuit includes elements
21
to
28
, and wires
31
to
35
each of which is connected between the elements. Elements
21
to
28
are electrically connected to wires
31
to
35
through pins P
1
to P
12
. Each of elements
21
,
24
,
27
,
28
consists of a flip-flop. It is assumed that information on an inter-pin delay time of each of elements in the circuit, a inter-pin delay time of each of wire in the circuit, etc. are beforehand stored in a delay analysis result display device.
It is now assumed that an operator inputs to the delay result display device a command to display a delay analysis result of the path between flip-flops
21
and
24
.
FIG. 12
shows an example of a circuit diagram which is displayed on a screen of the delay analysis result display device. In response to the command, the delay analysis result display device displays such a circuit as shown in
FIG. 12
, and also displays a delay analysis result of this path (not shown).
In
FIG. 12
, only elements
21
to
24
and wires
31
to
33
connected therebetween are illustrated. Further, at the same time, the delay analysis result only for the circuit shown in
FIG. 12
is displayed. An example of this type delay analysis system is disclosed in JPA-2-245879. This publication discloses as a prior art an analysis system comprising a CAD master file, an FF check program, an FF check result file, an analysis program, and a list.
According to the analysis system, circuit elements and wiring conditions stored in the CAD master file are used for path ready check between FFs (flip-flops) by an FF check program, the path ready check result thus obtained is outputted to the FF check result file, the data thus outputted are analyzed by batch process using an analysis program and the analysis result is output as a list. Among the members of the system, the FF check result file corresponds to the delay analysis result, and the list corresponds to the display device.
However, the conventional delay analysis result display device displays only a path which is obtained from the delay analysis result. That is, only elements
21
to
24
and wires
31
to
33
which are connected between the respective elements are displayed as shows in FIG.
12
. Therefore, even when the circuit correction is intended to be performed on the basis of the delay analysis result, it needs a large labor to perform the circuit correction because the situation of adjoining circuits is unknown.
That is, in order to examine the situation of the adjoining circuits, it is needed to examine the corresponding path or wire by making reference to a circuit diagram on a paper or on a screen of a circuit diagram display device or the like, whereby large time is needed for the circuit correction.
The system disclosed in JPA-2-245879 never teaches means for solving the above problem.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a delay analysis result display device which enables a user to recognize the situation of circuits adjoining to the path for which a delay analysis result is displayed.
According to the present invention, there is provided a delay analysis result display device which displays a delay time analysis result of each of electrical signals in a designated path in an electrical circuit, which comprises: delay time analysis result storage means for storing the delay time analysis result; circuit information storage means for storing circuit information containing the delay time of each of electrical signals of all paths in the electrical circuit; designator storage means for designating a wire between any elements in the designated path; and display means for displaying the delay time analysis result while adding into the designated path other wires which are not contained in the designated path, but contained in the electrical circuit and which are electrically connected to the designated wire, and displaying the delay time analysis result of each of electrical signals of the other wires.
According to the present invention, the display means displays the delay time analysis result of the designated path while adding another wire which is electrically connected to the designated wire and is not contained in the designated path.


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