Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-05-26
1999-02-23
Vo, Don N.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
370516, H04L 700
Patent
active
058752170
ABSTRACT:
A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
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Cadieux Kevin
Hartmann Paul R.
Pope Kevin
Applied Digital Access
Vo Don N.
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