Delay adjustment circuit and a clock generating circuit...

Details Delay adjustment circuit and a clock generating circuit... Delay adjustment circuit and a clock generating circuit...

2005-07-12

2005-07-12

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000, C327S276000

Reexamination Certificate

active

06918050

ABSTRACT:
The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array10for carrying out fine adjustment of the delay time interval of the input signal, capacitances60to63and70to73connected to the output side of a specified gate in the first gate array via first switching device40to43,a second gate array20for carrying out rough adjustment of the delay time interval of the input signal; and a control device30that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array20.

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Goto et al. “CMOS Programmable Delay Vernier”—Oct. 1994—Hewlett-Packard Journal—vol. 45, Issue 5, p. 51-58.

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