Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2006-10-24
2006-10-24
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S189011
Reexamination Certificate
active
07126842
ABSTRACT:
The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.
REFERENCES:
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5194759 (1993-03-01), El-Ayat et al.
patent: 5222066 (1993-06-01), Grula et al.
patent: 5272101 (1993-12-01), Forouhi et al.
patent: 5299152 (1994-03-01), Ishihara et al.
patent: 5311080 (1994-05-01), Britton et al.
patent: 5327024 (1994-07-01), Cox
patent: 5371422 (1994-12-01), Patel et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5469003 (1995-11-01), Kean
patent: 5490074 (1996-02-01), Agrawal et al.
patent: 5495181 (1996-02-01), Kolze
patent: 5504703 (1996-04-01), Bansal
patent: 5509128 (1996-04-01), Chan
patent: 5525923 (1996-06-01), Bialas, Jr. et al.
patent: 5537057 (1996-07-01), Leong et al.
patent: 5598109 (1997-01-01), Leong et al.
patent: 5611042 (1997-03-01), Lordi
patent: 5648913 (1997-07-01), Bennett et al.
patent: 5666322 (1997-09-01), Conkle
patent: 5671432 (1997-09-01), Bertolet et al.
patent: 5744979 (1998-04-01), Goetting
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5761140 (1998-06-01), Choi
patent: 5815004 (1998-09-01), Trimberger et al.
patent: 5850564 (1998-12-01), Ting et al.
patent: 5894228 (1999-04-01), Reddy et al.
patent: 5942914 (1999-08-01), Reddy et al.
patent: 5966027 (1999-10-01), Kapusta et al.
patent: 5994934 (1999-11-01), Yoshimura et al.
patent: 6005410 (1999-12-01), Laramie
patent: 6038627 (2000-03-01), Plants
patent: 6043677 (2000-03-01), Albu et al.
patent: 6049225 (2000-04-01), Huang et al.
patent: 6107822 (2000-08-01), Mendel et al.
patent: 6111448 (2000-08-01), Shibayama
patent: 6130551 (2000-10-01), Agrawal et al.
patent: 6150837 (2000-11-01), Beal et al.
patent: 6150841 (2000-11-01), Agrawal et al.
patent: 6150868 (2000-11-01), Kim et al.
patent: 6181174 (2001-01-01), Fujieda et al.
patent: 6205533 (2001-03-01), Margolus
patent: 6237124 (2001-05-01), Plants
patent: 6268743 (2001-07-01), Kaptanoglu
patent: 6286093 (2001-09-01), Chang et al.
patent: 6289068 (2001-09-01), Hassoun et al.
patent: 6289494 (2001-09-01), Sample et al.
patent: 6292016 (2001-09-01), Jefferson et al.
patent: 6300793 (2001-10-01), Ting et al.
patent: 6333666 (2001-12-01), Kim et al.
patent: 6338106 (2002-01-01), Vorbach et al.
patent: 6437650 (2002-08-01), Sung et al.
patent: 6567968 (2003-05-01), Kaptanoglu
patent: 6570798 (2003-05-01), McCollum
patent: 6570805 (2003-05-01), McCollum
patent: 6636930 (2003-10-01), Kaptanoglu
patent: 6990010 (2006-01-01), Plants
patent: 1 137 188 (2001-09-01), None
patent: 1 137 188 (2003-08-01), None
L. Ashby, “ASIC Clock Distribution Using a Phase Locked Loop (PLL),”Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, pp. P1-6.1-P1-6.3, Sep. 23-27, 1991.
“AV9170 Clock Synchronizer and Multiplier,” originally owned by AvaSem Corp, dated Nov. 1992, update version AV9170, Integrated Circuit Systems, Inc., pp. 1-11, Rev E Sep. 24, 1999.
“AV9170 Application Note-Clock Synchronizer and Mulitplier,” Integrated Circuit Systems, Inc. former AvaSem Corp., pp. 1-7, originally dated Jan. 1993, revision 9170AppRev111694, no date on publication.
U. Ko et al., “A 30-ps JITTER, 3.6 μs Locking, 3.3-Volt Digital PLL For CMOS Gate Arrays,”IEEE 1993 Custom Integrated Circuits Conference, pp. 23.3.1-23.3.4, Conf. Date: May 9-12, 1993.
A. Efendovich, et al. “Multi-frequency Zero-Jitter Delay-Locked Loop,”IEEE 1993 Custom Integrated Circuits Conference, pp. 27.1.1-27.1.4, Conf. Date: May 9-12, 1993.
R. Quinnell, Technical Ed., “Blending gate arrays with dedicated circuits sweentens ASIC development,”EDN, pp. 29-32, Mar. 31, 1994.
J. R. Schwank, Section II, “Basic Mechanisms of Radiation Effects in the Natural Space Environment” in “Radiation Effect in Commercial Electronics,”IEEE Nuclear and Space Radiation Effects Conference Short Course, pp. II-1 to II-87, Westin La Paloma Resort, Tuscon, Arizona, Jul. 18, 1994.
N. Haddad et al., Chapter IV, “Adapting Commercial Electronics to the Naturally Occurring Radiation Environment in Radiation Effect in Commercial Electronics,”IEEE Nuclear and Space Radiation Effects Conference Short Course, pp. IV-20 to IV-25, Westin La Paloma Resort, Tuscon, Arizona, Jul. 18, 1994.
J. Chen, “PLL-based clock systems span the system spectrum from green PCs to Alpha,”EDN, pp. 147-155, Nov. 9, 1995.
P. Sevalia, “Straightforward techniques cut jitter in PLL-based clock drivers,”EDN, pp. 119-125, Nov. 23, 1995.
D. Bursky, “Memories Hit New Highs and Clocks Run Jitter-Free,”Electronic Design, pp. 79-93, Feb. 19, 1996.
G. Messenger et al., Chapter 2, “Extraterrestrial SEU-Inducing Particles,”Single Event Phenomena, pp. 23-35, 74-85, Chapman & Hall a division of International Thomson Publishing, 1997.
Y. Lia et al., “Hierarchical Interconnection Structures For Field Programmable Gate Arrays,” IEEE Transaction on Very Large Scale (VLSI) Interaction Systems, vol. 5, No. 2, pp. 186-196, Jun. 1997.
Actel Corporation
Le Thong Q.
Sierra Patent Group Ltd.
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