Deflection-distortion correcting circuit

Details Deflection-distortion correcting circuit Deflection-distortion correcting circuit

2000-12-05

2002-07-23

Philogene, Haissa (Department: 2821)

Electric lamp and discharge devices: systems

Cathode ray tube circuits

Cathode-ray deflections circuits

C315S371000, C348S807000

Reexamination Certificate

active

06424103

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit for correcting distortion of an image on a screen in an image displaying apparatus having a cathode-ray tube, such as a display monitor.
BACKGROUND OF THE INVENTION
In an image displaying apparatus having a cathode-ray tube, such as a display monitor, an image produced on a screen through deflection of an electron beam has distortion (referred to as “deflection-distortion” hereinafter) depending on the form of the cathode-ray tube etc. Therefore, a deflection-distortion correcting circuit that generates a deflection-distortion correcting signal is used to adjust the extent of deflection and correct the deflection-distortion of an image on a screen. The above-described deflection-distortion correcting signal is generated by an analog circuit, however, it is not necessarily possible to obtain a deflection-distortion correcting signal having the desired accuracy. Accordingly, with the aim of improving the accuracy of such a deflection-distortion correcting signal, a deflection-distortion correcting circuit has been proposed that generates a deflection-distortion correcting signal based on digital data.
FIG. 10
is a block diagram of such a deflection-distortion correcting circuit. The deflection-distortion correcting circuit shown in
FIG. 10
, described in Japanese Unexamined Patent Publication No. 5-328163, generates a deflection-distortion correcting signal on the basis of digital data. In
FIG. 10
, there is shown a horizontal-deflection circuit
5
, a horizontal-deflection power supplying circuit
6
of the series type, a horizontal-deflection current output circuit
7
, a horizontal-deflection coil
8
, a deflection-distortion .correcting circuit
21
, a period-discriminating circuit
22
, a period/N-generating circuit
23
, an output-level control circuit
24
, a counter circuit
25
, a D/A conversion circuit
26
, and an inverting/amplifying circuit
27
.
The operation of the above deflection-distortion correcting circuit
21
shown in
FIG. 10
will be explained below. The counter circuit
25
is reset by level change of a vertical synchronizing signal, and starts a count of clock pulses produced by frequency-dividing a reference clock in the period/N-generating circuit
23
. The count data (digital data) of the counter circuit
25
is converted into an analog signal by the D/A conversion circuit
26
, inverted in signal polarity by the inverting/amplifying circuit
27
as necessary, and is adjusted in signal amplitude (Here, it is assumed that the signal polarity is not inverted, and the analog signal output from the inverting/amplifying circuit
27
increases linearly). The analog signal which is generated from this digital data and increases linearly is output from the deflection-distortion correcting circuit
21
to the horizontal-deflection power supplying circuit
6
as a deflection-distortion correcting signal.
The horizontal-deflection power supplying circuit
6
has an internal structure as shown in FIG.
2
. The source voltage V
out
which the horizontal-deflection power supplying circuit
6
supplies to the horizontal-deflection current output circuit
7
is modulated by the deflection-distortion correcting signal S
b
input from the deflection-distortion correcting circuit
21
. The horizontal-deflection current output circuit
7
generates a horizontal-deflection current using the voltage V
out
modulated by the deflection-distortion correcting signal S
b
as its electric power, and supplies it to the coil
8
. The coil
8
generates a horizontal-deflection magnetic field according to the supplied horizontal-deflection current. The envelope characteristic of the peak values of the above-described horizontal-deflection current varies according to the modulated source voltage V
out
. Thus, deflection-distortion in that a monitor screen is distorted to a trapezoidal shape can be corrected.
FIG.
11
(
a
) shows a waveform of the deflection-distortion correcting signal S
b
generated by the deflection-distortion correcting circuit
21
of
FIG. 10
, and the source voltage V
out
modulated by this deflection-distortion correcting signal S
b
. FIG.
11
(
b
) shows a waveform of the deflection-distortion correcting signal S
b
generated by the deflection-distortion correcting circuit
21
, and the source voltage V
out
modulated by this deflection-distortion correcting signal S
b
, in a case where a vertical blanking signal is used instead of the vertical synchronizing signal in FIG.
10
. The vertical blanking signal is a signal whose level during an image display period (including horizontal blanking periods) over which a video signal exists is different from that during a vertical blanking period over which no image signal exists, to enable detecting a vertical blanking period. FIG.
11
(
c
) shows a monitor screen corrected by the source voltage V
out
modulated by the deflection-distortion correcting signal S
b
of FIG.
11
(
a
) or
11
(
b
). In FIG.
11
(
a
) and FIG.
11
(
b
), the dotted line represents a waveform of the deflection-distortion correcting signal S
b
which increases linearly, and the source voltage V
out
modulated normally by this deflection-distortion correcting signal, and the solid line represents a waveform of the source voltage V
out
distorted by parasitic inductance in the horizontal-deflection power supplying circuit
6
. In FIG.
11
(
c
), the chain line represents a monitor screen distorted to a trapezoidal shape before correction, the dotted line represents a monitor screen corrected by the source voltage modulated normally, and the solid line represents a monitor screen corrected by the distorted source voltage.
If the source voltage V
out
is normally modulated as shown by the dotted line in FIG.
11
(
a
) in the horizontal-deflection power supplying circuit
6
according to the deflection-distortion correcting signal S
b
which increases linearly, the monitor screen distorted to the trapezoidal shape as shown by the chain line in FIG.
11
(
c
) is corrected normally as shown by the dotted line in FIG.
11
(
c
).
However, the above-described conventional deflection-distortion correcting circuit involves a problem, which will be explained below.
FIG. 12
is an equivalent circuit diagram of the power supplying circuit
6
of the series type in a case where parasitic inductance is not negligible. In
FIG. 12
, the reference numerals identical to those in
FIG. 2
represent the same elements. The horizontal-deflection power supplying circuit
6
of
FIG. 12
differs from the horizontal-deflection power supplying circuit
6
of
FIG. 2
in that an inductive load
30
appears between an emitter electrode of a transistor
16
and an output terminal of the source voltage V
out
due to the parasitic inductance. Although inductance components (parasitic inductance) of capacitors
18
and
19
and a wiring pattern are negligible for a low frequency signal, they are not negligible for a high frequency signal, and therefore, the inductive load
30
appears as shown in FIG.
12
.
In the deflection-distortion correcting circuit
21
of
FIG. 10
, the moment the counter circuit
25
is reset by the vertical synchronizing signal, the digital data changes instantaneously from the maximum value to the minimum value, and therefore the deflection-distortion correcting signal as well changes instantaneously from the maximum value to the minimum value. Accordingly, the deflection-distortion correcting signal includes a high frequency component. When the deflection-distortion correcting signal having such a high frequency component is input into the horizontal-deflection power supplying circuit
6
, the above-described inductance component in the horizontal-deflection power supplying circuit
6
cannot be neglected, and the inductive load
30
appears as a factor in the horizontal-deflection power supplying circuit
6
as shown in FIG.
12
.
When the inductive load
30
appears, the source voltage V
out
for horizontal deflection is not normally modulated according to the deflection-dis

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