Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-11
2009-02-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S002000, C708S607000
Reexamination Certificate
active
07487486
ABSTRACT:
The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
REFERENCES:
patent: 2004/0243953 (2004-12-01), Ramachandran et al.
patent: 2004/0243954 (2004-12-01), Devgan et al.
patent: 2005/0066296 (2005-03-01), Visweswariah
patent: 2005/0091298 (2005-04-01), Kalafala et al.
Celik Mustafa
Le Jiayong
Li Xin
Pileggi Lawrence
Lin Aric
Neville Deborah
Siek Vuthe
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