Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-04-10
2003-05-27
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S100000
Reexamination Certificate
active
06570795
ABSTRACT:
TECHNICAL FIELD
This invention relates to memory devices.
BACKGROUND
Conventional read-only memory (ROM) circuits are implemented as special-purpose integrated circuits for the permanent storage of program instructions and data. For example, a ROM circuit can be manufactured with specific instructions for the operation of a computer system.
Typically, a ROM circuit consists of an array of memory cells on a semiconductor, and each memory cell has a transistor that is fabricated to indicate a logic “one” or a logic “zero” based on how the semiconductor is implanted to create the transistor. The data is permanently stored with a memory cell, and it cannot then be erased or altered electrically. Each of the transistors can be formed so as to have one of the two predetermined logic values.
A programmable ROM (PROM) circuit is designed with memory cells having programmable memory components that can be programmed after the semiconductor chip has been manufactured. The memory cells of a PROM device are programmed with data (e.g., a logic one or a logic zero) when the instructions are burned into the chip. This is accomplished by forming contacts that define the threshold voltage levels near the end of the manufacturing process, or after the manufacturing process. When a PROM device is programmed, the device can be implemented like a conventional ROM chip in that the data cannot be electrically altered.
A semiconductor memory device is typically fabricated with extra rows and columns of memory cells that are used to replace rows and/or columns having defective memory cells that cannot be repaired. A single defective memory cell can result in thousands of otherwise non-defective memory cells being unusable. Further, the extra rows and columns of memory cells increase manufacturing expenses to account for defective memory cells such that the memory device can yield its designed capacity. If a memory device has more defective memory cells than can be replaced with the redundant rows and columns, the entire memory device is unusable for its intended application.
Due to the costs of fabricating semiconductor devices, and the design of smaller integrated circuit-based electronic devices, there is an ever-present need to provide non-volatile memory circuits that take up less space, have improved memory storage capacity, and are inexpensive to manufacture.
SUMMARY
A memory device includes memory components that represent a logic value corresponding to a data bit in a bit sequence. A defective memory component in the memory device represents a data bit in the bit sequence. An additional memory component in the memory device represents an encode bit of the bit sequence, where the encode bit indicates whether the bit sequence is inverted.
REFERENCES:
patent: 3582908 (1971-06-01), Koo
patent: 3863231 (1975-01-01), Taylor
patent: 4442507 (1984-04-01), Roesner
patent: 5539697 (1996-07-01), Kim et al.
Anderson Daryl
Fricke Peter
Van Brocklin Andrew L.
Hewlett--Packard Development Company, L.P.
Lebentritt Michael S.
Phung Anh
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