Defective memory cell address detecting circuit

Details Defective memory cell address detecting circuit Defective memory cell address detecting circuit

1998-08-21

1999-10-26

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

365154, 365203, 3652257, G11C 700

Patent

active

059739690

ABSTRACT:
In a semiconductor memory including a memory cell array and a redundant memory cell array, a defective memory cell address detecting circuit includes a precharge transistor for precharging a COMP signal line of outputting a signal indicative of whether or not an input address is an address of the defective memory cell, and a plurality of detection transistors connected in parallel to the COMP signal line. Each of the detection transistors has a gate connected to receive, through a wired connection, a corresponding bit and its inverted bit of bits of the input address signal. Thus, the number of detection transistors connected in parallel to the COMP signal line can be reduced to a half of the number required in the prior art.

REFERENCES:
patent: 5586075 (1996-12-01), Miwa
patent: 5742547 (1998-04-01), Lee
patent: 5768198 (1998-06-01), Movoo
patent: 5777931 (1998-07-01), Kwon et al.
patent: 5825698 (1998-10-01), Kim et al.

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