Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2003-05-14
2004-10-26
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S201000, C365S189070, C365S200000, C365S230080, C365S096000, C365S094000
Reexamination Certificate
active
06809982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as SDRAM (Synchronous Dynamic Random Access Memory), and more particularly to a semiconductor memory device that uses capacitor fuses to effect a one-bit remedy, and to a method of remedying a defective cell.
2. Description of the Related Art
Semiconductor memory devices such as DRAM are provided with a large number of memory cells, and it is therefore inevitable that some memory cells will be defective memory cells, i.e., cells that do not function properly. Discarding the entire semiconductor memory device as a defective product when such a defective memory cell occurs increases the cost of fabricating the semiconductor memory device, and various methods have therefore been proposed as methods of remedying defective cells that occur.
When a defective cell is discovered in an investigation of a semiconductor memory device in the wafer state, the defective cell is replaced by a redundant cell that has been prepared in advance to maintain the overall integrity of the semiconductor memory device. To effect this replacement, it is necessary to store the address of the defective cell, and fuse elements are used to store the address of this defective cell. Fuse elements include elements that normally function as resistor elements but that blow out upon the flow of an overcurrent and thus enter an insulating state, and elements that are cut by the irradiation of a laser beam.
However, because the formation of a resistor element requires a certain amount of surface area, the use of these resistor elements as fuse elements raises the problem of increase in the layout area with increase in the number of fuse elements that are used. On the other hand, once a semiconductor memory device has been packaged, a laser beam cannot be irradiated to cut the fuse elements.
Capacitor fuses are therefore used for remedying defective cells that are discovered after packaging. A capacitor fuse is an element in which the application of a high voltage across two electrodes that are normally in an insulating state can bring about a dielectric breakdown that destroys a dielectric film and thus place the two electrodes in a connected state. By using such a capacitor fuse, one fuse element can be realized in the same layout area that is required for one memory cell. In addition, cutting of a capacitor fuse requires only the application of a high voltage to the capacitor fuse, and it is therefore possible to cut a capacitor fuse after a semiconductor memory device has been packaged.
In contrast to a normal fuse element, which functions as a resistor element before cutting and then enters an open state after cutting, a capacitor fuse functions as a capacitor with an open state established between two terminals before cutting and then functions as a resistor element after cutting.
As a method of remedying defective cells after a semiconductor memory device has been packaged, a method has been proposed in recent years that uses a one-bit remedy employing the above-described capacitor fuse. When a defective cell is discovered after a semiconductor memory device has been packaged, this one-bit remedy method stores the data that was to be stored in the defective cell in a storage circuit such as a latch circuit.
In this one-bit remedy, the discovery of a defective cell does not result in the separate storage of only the data that are stored in the defective cell. Instead, a unit of cells that are activated by a column selection circuit (Y-switch circuit) are taken as the unit of simultaneous remedy, and all of the data that are stored in all memory cells that are included in this simultaneous remedy unit are separately stored.
FIG. 1
shows the construction of a semiconductor memory device of the prior art that effects this type of one-bit remedy. As shown in
FIG. 1
, this semiconductor memory device of the prior art is provided with memory cell array
10
that is composed of a plurality of memory cells, row decoder
20
, column decoder
30
, comparison circuit
40
, address buffer circuit
150
, and capacitor fuse blocks
80
1
-
80
n
.
An external address signal that is used in, for example DRAM, is composed of alternately arranged row addresses and column addresses. As a result, address buffer circuit
150
not only divides external address signal
1
that is applied from outside the semiconductor memory device into row address signal
2
and column address signal
3
, but also holds row address signal
2
and column address signal
3
until external address signal
1
designates the next address.
FIG. 2
shows a specific composition of this address buffer circuit
150
. As shown in
FIG. 2
, address buffer circuit
150
is provided with inverter circuits
51
,
52
,
55
-
57
,
58
,
59
,
62
-
64
,
86
, and
87
; p-channel MOS transistors
53
and
60
; and n-channel MOS transistors
54
and
61
. This composition that is shown in
FIG. 2
is for a one-bit portion of the address signal, and in an actual address buffer circuit, the circuit structure that is shown in
FIG. 2
is provided in a number equal to the number of bits of the address signal.
In addition, row address latch signal
5
and column address latch signal
6
are applied as input to this address buffer circuit
150
as shown in
FIG. 1
, and when external address signal
1
indicates a row address, row address latch signal
5
becomes high level for a fixed interval; and when external address signal
1
indicates a column address, column address latch signal
6
becomes high level for a fixed interval.
Inverter circuits
86
and
87
invert row address latch signal
5
and column address latch signal
6
, respectively, and supply the result as output. Inverter circuits
51
and
58
invert external address signal
1
and supply the result as output. Inverter circuit
52
inverts the output of inverter circuit
86
and supplies the result to the gate of n-channel MOS transistor
54
. Inverter circuit
59
inverts the output of inverter circuit
87
and supplies the result to the gate of n-channel MOS transistor
61
.
P-channel MOS transistor
53
receives the output of inverter circuit
86
at its gate, turns on when row address latch signal
5
becomes high level and the output of inverter circuit
86
becomes low level, and supplies the output of inverter circuit
51
to data holding unit that is composed of inverter circuits
55
and
56
. N-channel MOS transistor
54
receives the output of inverter circuit
52
at its gate, and, as with p-channel MOS transistor
53
, turns on when row address latch signal
5
becomes high level and supplies the output of inverter circuit
51
to a data holding unit that is composed of inverter circuits
55
and
56
.
Inverter circuits
55
and
56
each invert the output of the other and thus hold signals that are transmitted by way of p-channel MOS transistor
53
and n-channel MOS transistor
54
. Inverter circuit
57
inverts the value that is held by inverter circuits
55
and
56
and supplies the result as row address signal
2
.
P-channel MOS transistor
60
receives the output of inverter circuit
87
at its gate, turns on when column address latch signal
6
becomes high level and the output of inverter circuit
87
becomes low level, and supplies the output of inverter circuit
58
to the data holding unit that is composed of inverter circuits
62
and
63
. N-channel MOS transistor
61
receives the output of inverter circuit
59
at its gate, and, similar to p-channel MOS transistor
60
, turns on when column address latch signal
6
becomes high level and supplies the output of inverter circuit
58
to the data holding unit that is composed of inverter circuits
62
and
63
.
Inverter circuits
62
and
63
each invert the output of the other and thereby hold the signal that is transmitted by way of p-channel MOS transistor
60
and n-channel MOS transistor
61
. Inverter circuit
64
inverts the value that is held by inverter circuits
62
and
63
and supplies the resul
Choate Hall & Stewart
Elpida Memory Inc.
Tran Andrew Q.
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